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5,707 Views
Registered: ‎08-21-2008

IDELAYCTRL generation by MIG

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Hello.

I am trying to implement DDRII controller.

The UCF generated by MIG contains 4 IDELAYCTRLs whereas max C_NUM_IDELAYCTRL parameter value is 3 in EDK DDRII GUI. That means i can only instantiate 3 IDELAYCTRLs in EDK.

So what about the fourth one and if it is true then which 3 i have to use which one to reject??

 

Waiting for your valuable suggestions.

 

Regards. 

Best of luck.
--
Unlimited in my Limits.
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Observer sbonafede
Observer
7,015 Views
Registered: ‎08-07-2008

Re: IDELAYCTRL generation by MIG

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I, too, just ran into this when messing around with a custom DDR2 MIG compatible design for a V5FX design.  (The peripheral: ppc440mc_ddr2_v2_00_a)

 

See page 5 of DDR2 Memory Controller for PowerPC 440 Processors [DS567 (v1.3)].

 

Looking at the verilog, there's a generate statement to instantiate the idelay controllers and so it should be possible to hack the mpd file to allow for more than 3 IDELAYCTRL...

 

EDIT:  Just noticed that the original poster is implementing a DDRII controller and I'm implementing a DDR2 controller.

Message Edited by sbonafede on 05-11-2009 04:12 PM
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Visitor adetel
Visitor
5,705 Views
Registered: ‎05-06-2009

Re: IDELAYCTRL generation by MIG

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Hi,

 

When using several IDELAYCTRL only one has to be constrained leave the others unconstrained.

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Xilinx Employee
Xilinx Employee
5,700 Views
Registered: ‎08-07-2007

Re: IDELAYCTRL generation by MIG

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Hi,

 

Where do you get the information that the max value of C_NUM_IDELAYCTRL is '3"? I can see it supports upto 16 in MPD file.

 

-XF

 

 

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Observer sbonafede
Observer
7,016 Views
Registered: ‎08-07-2008

Re: IDELAYCTRL generation by MIG

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I, too, just ran into this when messing around with a custom DDR2 MIG compatible design for a V5FX design.  (The peripheral: ppc440mc_ddr2_v2_00_a)

 

See page 5 of DDR2 Memory Controller for PowerPC 440 Processors [DS567 (v1.3)].

 

Looking at the verilog, there's a generate statement to instantiate the idelay controllers and so it should be possible to hack the mpd file to allow for more than 3 IDELAYCTRL...

 

EDIT:  Just noticed that the original poster is implementing a DDRII controller and I'm implementing a DDR2 controller.

Message Edited by sbonafede on 05-11-2009 04:12 PM
5,659 Views
Registered: ‎08-21-2008

Re: IDELAYCTRL generation by MIG

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Hi XF.

I don't know from which MPD you are telling this but i am attaching a sanpshot with this.

You can see at the top blue line there is written PPC440mc_ddr2_v2_1_0.mpd

Whereas the highlited portion tells you that max value of C_NUM_IDELAYCTRL parameter is 3

I am using version 10.1 with SP3 

 

Waiting for your valuable inputs.

 

Regards. 

Best of luck.
--
Unlimited in my Limits.
untitled.bmp
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5,643 Views
Registered: ‎08-21-2008

Re: IDELAYCTRL generation by MIG

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Hello.

all the errors are gone just by manually changing the idelay_ctrl.v and  the corresponding MPD file for DDR2.

Changes are done to extend the max value of C_NUM_IDELAYCTRL parameter from 3 to 4.

The moment i included the extra IDELAYCTRL everything was mapped successfully and bit stream generation is complete.

I don't understand one thing that is why EDK limited the number of IDELAYCTRL parameters.

 

thanks for all the co-operation provided by you people.

 

Regards. 

Best of luck.
--
Unlimited in my Limits.
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Xilinx Employee
Xilinx Employee
5,633 Views
Registered: ‎08-07-2007

Re: IDELAYCTRL generation by MIG

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I thought you are talking about MPMC.

 

-XF

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