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diama13
Observer
Observer
2,461 Views
Registered: ‎02-10-2011

IP Core Axi4 Axi Lite

I have created an axi slave burst core(axi4) with create and import peripheral and i would like to add some registers which can be written and read through axi lite. Can anyone help me???? 

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4 Replies
diama13
Observer
Observer
2,449 Views
Registered: ‎02-10-2011

Could anyone help me?

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dgisselq
Scholar
Scholar
594 Views
Registered: ‎05-21-2015

Consider this blog entry describing how to generate an AXI-lite peripheral that passes a formal verification check.  While you could ask Vivado to generate this example IP, as of Vivado 2018.3 it doesn't pass the check.

Dan

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ritakur
Xilinx Employee
Xilinx Employee
573 Views
Registered: ‎09-01-2014

Please refer to the “Creating a New AXI4 Peripheral” section to create an AXI IP with register included, then you can modify the generated HDL source to add custom logic and make it as a custom IP.
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug1118-vivado-creating-packaging-custom-ip.pdf
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dgisselq
Scholar
Scholar
563 Views
Registered: ‎05-21-2015

@ritakur,

Does this mean that Xilinx has finally fixed the bug in their AXI-lite core?  As of 2018.3, it hadn't been fixed.

Dan

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