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Adventurer
Adventurer
4,178 Views
Registered: ‎03-19-2009

IP is not updated

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Hi Everybody,

 

since yesterday the custom logic in my design is not updated. 

 

I am changing the user_logic.vhd file, deleting the ip in my design and importing with CIP but the changes do not occur.

Before I had also the feeling, that the changes I wanted did not happen but now I can see it with Chipscope.

 

I even logged off from my PC, in case it could help. 

 

 

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Xilinx Employee
Xilinx Employee
5,108 Views
Registered: ‎08-07-2007

Re: IP is not updated

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Hi,

 

check if the option ARCH_SUPPORT_MAP has been set to development in MPD file.

 

If it doesn't help, clean the cached netlist file in implementation/cache directory.

 

-XF

3 Replies
Xilinx Employee
Xilinx Employee
5,109 Views
Registered: ‎08-07-2007

Re: IP is not updated

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Hi,

 

check if the option ARCH_SUPPORT_MAP has been set to development in MPD file.

 

If it doesn't help, clean the cached netlist file in implementation/cache directory.

 

-XF

Adventurer
Adventurer
4,170 Views
Registered: ‎03-19-2009

Re: IP is not updated

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Hi xiaofeip,

 

I cannot find ARCH_SUPPORT_MAP in my mpd file.Is it maybe in some other file?

 

For now I have deleted the folder implementation. 

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Xilinx Employee
Xilinx Employee
4,165 Views
Registered: ‎08-07-2007

Re: IP is not updated

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If it's not in the MPD file, you can add one manually. Find the psf_rm.pdf for details.

 

With this option set to "development", the core will be synthesized every time PlatGen is run. The cached netlist won't be used, so that you don't have to clean the netlists.

 

-XF