cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
1keith1
Participant
Participant
10,172 Views
Registered: ‎02-17-2014

(ISE 14.7) PlanAhead Remove UCF & Pass Manually

I am getting this error: 

http://www.xilinx.com/support/answers/52991.html

 

And I am trying to follow the solution. The error arises from using XPS to create a hardware platform, and then trying to implement it in planahead.


I tried recreating the project, which did not work. Now I am trying to follow where it says:

 

"

  • Another option is to remove the UCF from the PlanAhead project, and instead pass the UCF file through the -uc switch in the NGDBuild options.
    With this option, the GUI will not show the I/O ports that are fixed, as the project does not have an associated UCF to determine which sites are "fixed".
    However the implementation tools will see the original UCF constraints and process them as it would when using Project Navigator or the ISE command line flow."

But I don't understand how to remove the UCF and then pass it manually.

 

Untitled.png

0 Kudos
9 Replies
tusharvi
Explorer
Explorer
10,146 Views
Registered: ‎04-28-2015

Hi @1keith1,

Yes, the ucf file can be passed in the "more options" as you pointed.

Format:
-uc <ucf_file_name>.ucf


Please note that the ucf_file needs to be in the local directory. in the above method


Regards,

Tushar

----------------------------------------------------------------------------------------------------------------------------
Please mark the post as an answer ("Accept as solution") in case it helped resolve your query.
Give kudos in case a post guided you to the solution.
This will help others in the long run

0 Kudos
htsvn
Xilinx Employee
Xilinx Employee
10,124 Views
Registered: ‎08-02-2007

hi,

 

refer to this snapshot.

 

--hs

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
Capture.JPG
0 Kudos
1keith1
Participant
Participant
10,116 Views
Registered: ‎02-17-2014

I see. Unfortunately this did not fix my problem like the solution said it would.

 

I am still seeing these errors:

 

Capture.PNG

 

weird since the pins thhese are on are clock capable pins.

 


#LVDS RX
NET rx_0_d_clk_pin LOC = AC40 | IOSTANDARD = LVCMOS33; #ROUT 1

NET rx_1_d_clk_pin LOC = AD40 | IOSTANDARD = LVCMOS33; #ROUT 2

NET rx_2_d_clk_pin LOC = AC39 | IOSTANDARD = LVCMOS33; #ROUT 3

NET rx_3_d_clk_pin LOC = AC38 | IOSTANDARD = LVCMOS33; #ROUT 4

 

I will probably end up setting CLOCK_DEDICATED_ROUTE = FALSE; if i can't figure this out, since that solves it.

 

0 Kudos
1keith1
Participant
Participant
10,115 Views
Registered: ‎02-17-2014

Hm actually looks like even CLOCK_DEDICATED_ROUTE to False does not solve these errors. I'm at a loss.

0 Kudos
htsvn
Xilinx Employee
Xilinx Employee
10,111 Views
Registered: ‎08-02-2007

hi,

 

it looks that they are being picked up from NCF. Do you have any netlist which has these constraints being locked?

 

which device are you using with the complete package?

 

--hs

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
1keith1
Participant
Participant
10,097 Views
Registered: ‎02-17-2014

This is a Microblaze Project, the .ncf seems to be generated from and identical to the .ucf.

 

I am using a Virtex5, xc5vfx130tff1738-1.

 

I just tried making the signals ibufs:

(*buffer_type = "ibuf"*) input clkin;

 

But even after doing this in the microblaze peripheral code (I'm using 4 of these peripherals, hence the 4 critical warnings) I still get constraint 18-5 errors about a BUFG, when I am not using one.

0 Kudos
htsvn
Xilinx Employee
Xilinx Employee
10,084 Views
Registered: ‎08-02-2007

hi,

 

would that be possible to attach the project for further debug?

 

--hs

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
1keith1
Participant
Participant
10,072 Views
Registered: ‎02-17-2014

I will private message it to you.

0 Kudos
1keith1
Participant
Participant
10,048 Views
Registered: ‎02-17-2014

Looks like I have to post it here. Attached is the project.

 

Under 'UNIBUS.srcs\sources_1\edk\system\pcores\rx_v1_00_a\hdl\verilog\user_logic.v' is the peripheral code that has the pins causing the critical warnings.

 

despite setting '(*buffer_type = "ibuf"*) input clkin;' the input is still treated as a BUFGP.

 

 

0 Kudos