UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer shamanth
Observer
5,048 Views
Registered: ‎03-09-2008

ISE-XPS integration

Hi,

 

Can anyone please tell me how to import an IP generated in Xilinx ISE (8.1) using the Xilinx CORE Generator into an XPS project(8.1)?

 

Thank you.

 

Shamanth

 

 

Tags (4)
0 Kudos
2 Replies
Visitor adetel
Visitor
5,012 Views
Registered: ‎05-06-2009

Re: ISE-XPS integration

Hi,

 

First you should look in the EDK IP library if the IP you've generated under coregen is not available.

 

If it is not, then you will have to create a custom peripheral in EDK.

It will encapsulate your IP in a peripheral that will allow the processor to get access to the internal ressources of your IP using bus registers access or bus RAM access or more.

 

Custom peripherals are very powerfull and have lots of capabilities, check it out.

 

Start with EDK => Hardware => Create or import Peripheral.

0 Kudos
Observer shamanth
Observer
4,986 Views
Registered: ‎03-09-2008

Re: ISE-XPS integration

I first "Created" a peripheral in EDK , keeping the option for ISE and XST checked(generate ISE and XST files to implement using XST flow).

 

The saved my coregen project created in ISE in the "projnav" folder in "devl" of the "pcores" folder of my module since that is where XPS seems to store the ISE files.

 

Then I instantiated the coregen vhdl module in "userlogic.vhd" and also updated the .pao file for the library hierarchy.

 

Now I will "Import" the peripheral and check if it works!

 

Thank you.

 

Shamanth

0 Kudos