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Observer thobmei
Observer
10,128 Views
Registered: ‎05-28-2010

Import Periferal in XPS

Jump to solution

This is might an silly Question but i have huge problems importing my IPIF Periferals in XPS 11.4.

 

At first I generated an Template (v1.00.a)

then I added my logic

after that I tried 2 import my logic.

In the Impot Dialog i choose an higher Versions Number ...for example 1.01.a

in the next window I selected vhl source files

in the next Step i used the pao file located with the Autogenerated Themplate ...

 

Then the Import Wizzard shows me the HDL Analysis Information ....

everything looks good sofar

but when i Press next I'm toold that no vhdl Files are Compiled into the current  logical library called XXX_v1.01.a

 

So I tried to add the vhdl Files Manually to the Library XXX_1.01.a ....

but then the impoter gives back an HDL parsing Error ...

 

Please Tell me what im doing wrong here ...

 

Parsing PAO project file successfully ...

Analyzing HDL source files ...

Analyzing HDL source files successfully ...

HDL language for the peripheral (top level) design unit my_timer is vhdl ...

WARNING:EDK:2221 - Project file D:\thobmei\Examplebackup\pcores/my_timer.prj

already exists, will be overwrite and removed afterward ...

INFO:EDK:948 - Create temparary xst project file:

D:\thobmei\Examplebackup\pcores/my_timer.prj

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

proc_common_pkg.vhd" in Library proc_common_v3_00_a.

Package <proc_common_pkg> compiled.

Package body <proc_common_pkg> compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

or_muxcy.vhd" in Library proc_common_v3_00_a.

Entity <or_muxcy> compiled.

Entity <or_muxcy> (Architecture <implementation>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

family_support.vhd" in Library proc_common_v3_00_a.

Package <family_support> compiled.

Package body <family_support> compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

counter_f.vhd" in Library proc_common_v3_00_a.

Entity <counter_f> compiled.

Entity <counter_f> (Architecture <imp>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

pselect_f.vhd" in Library proc_common_v3_00_a.

Entity <pselect_f> compiled.

Entity <pselect_f> (Architecture <imp>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

or_gate128.vhd" in Library proc_common_v3_00_a.

Entity <or_gate128> compiled.

Entity <or_gate128> (Architecture <imp>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

ipif_pkg.vhd" in Library proc_common_v3_00_a.

Package <ipif_pkg> compiled.

Package body <ipif_pkg> compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/h

dl/vhdl/plb_address_decoder.vhd" in Library plbv46_slave_single_v1_01_a.

Entity <plb_address_decoder> compiled.

Entity <plb_address_decoder> (Architecture <IMP>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/h

dl/vhdl/plb_slave_attachment.vhd" in Library plbv46_slave_single_v1_01_a.

Entity <plb_slave_attachment> compiled.

Entity <plb_slave_attachment> (Architecture <implementation>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl

/vhdl/interrupt_control.vhd" in Library interrupt_control_v2_01_a.

Entity <interrupt_control> compiled.

Entity <interrupt_control> (Architecture <implementation>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/h

dl/vhdl/plbv46_slave_single.vhd" in Library plbv46_slave_single_v1_01_a.

Entity <plbv46_slave_single> compiled.

Entity <plbv46_slave_single> (Architecture <implementation>) compiled.

Compiling vhdl file

"D:/thobmei/Examplebackup/pcores/my_timer_v1_00_a/hdl/vhdl/my_timer.vhd" in

Library my_timer_v1_01_a.

ERROR:HDLParsers:3317 -

"D:/thobmei/Examplebackup/pcores/my_timer_v1_00_a/hdl/vhdl/my_timer.vhd" Line

75. Library my_timer_v1_00_a cannot be found.

ERROR:HDLParsers:3014 -

"D:/thobmei/Examplebackup/pcores/my_timer_v1_00_a/hdl/vhdl/my_timer.vhd" Line

76. Library unit my_timer_v1_00_a is not available in library

my_timer_v1_01_a.

WARNING:HDLParsers:3481 - Library my_timer_v1_01_a has no units. Did not save

reference file "xst/my_timer_v1_01_a/hdllib.ref" for it.

ERROR:EDK:2121 - Parse Errors encountered in HDL source

WARNING:EDK:2579 - Unable to delete temparary project file

D:\thobmei\Examplebackup\pcores\my_timer.prj : 13

HDL language for the peripheral (top level) design unit my_timer is vhdl ...

WARNING:EDK:2221 - Project file D:\thobmei\Examplebackup\pcores/my_timer.prj

already exists, will be overwrite and removed afterward ...

INFO:EDK:948 - Create temparary xst project file:

D:\thobmei\Examplebackup\pcores/my_timer.prj

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

proc_common_pkg.vhd" in Library proc_common_v3_00_a.

Package <proc_common_pkg> compiled.

Package body <proc_common_pkg> compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

or_muxcy.vhd" in Library proc_common_v3_00_a.

Entity <or_muxcy> compiled.

Entity <or_muxcy> (Architecture <implementation>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

family_support.vhd" in Library proc_common_v3_00_a.

Package <family_support> compiled.

Package body <family_support> compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

counter_f.vhd" in Library proc_common_v3_00_a.

Entity <counter_f> compiled.

Entity <counter_f> (Architecture <imp>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

pselect_f.vhd" in Library proc_common_v3_00_a.

Entity <pselect_f> compiled.

Entity <pselect_f> (Architecture <imp>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

or_gate128.vhd" in Library proc_common_v3_00_a.

Entity <or_gate128> compiled.

Entity <or_gate128> (Architecture <imp>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

ipif_pkg.vhd" in Library proc_common_v3_00_a.

Package <ipif_pkg> compiled.

Package body <ipif_pkg> compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/h

dl/vhdl/plb_address_decoder.vhd" in Library plbv46_slave_single_v1_01_a.

Entity <plb_address_decoder> compiled.

Entity <plb_address_decoder> (Architecture <IMP>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/h

dl/vhdl/plb_slave_attachment.vhd" in Library plbv46_slave_single_v1_01_a.

Entity <plb_slave_attachment> compiled.

Entity <plb_slave_attachment> (Architecture <implementation>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl

/vhdl/interrupt_control.vhd" in Library interrupt_control_v2_01_a.

Entity <interrupt_control> compiled.

Entity <interrupt_control> (Architecture <implementation>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/h

dl/vhdl/plbv46_slave_single.vhd" in Library plbv46_slave_single_v1_01_a.

Entity <plbv46_slave_single> compiled.

Entity <plbv46_slave_single> (Architecture <implementation>) compiled.

Compiling vhdl file

"D:/thobmei/Examplebackup/pcores/my_timer_v1_00_a/hdl/vhdl/user_logic.vhd" in

Library my_timer_v1_01_a.

Entity <user_logic> compiled.

Entity <user_logic> (Architecture <IMP>) compiled.

Compiling vhdl file

"D:/thobmei/Examplebackup/pcores/my_timer_v1_00_a/hdl/vhdl/my_timer.vhd" in

Library my_timer_v1_01_a.

ERROR:HDLParsers:3317 -

"D:/thobmei/Examplebackup/pcores/my_timer_v1_00_a/hdl/vhdl/my_timer.vhd" Line

75. Library my_timer_v1_00_a cannot be found.

ERROR:HDLParsers:3014 -

"D:/thobmei/Examplebackup/pcores/my_timer_v1_00_a/hdl/vhdl/my_timer.vhd" Line

76. Library unit my_timer_v1_00_a is not available in library

my_timer_v1_01_a.

ERROR:EDK:2121 - Parse Errors encountered in HDL source

WARNING:EDK:2579 - Unable to delete temparary project file

D:\thobmei\Examplebackup\pcores\my_timer.prj : 13

HDL language for the peripheral (top level) design unit my_timer is vhdl ...

WARNING:EDK:2221 - Project file D:\thobmei\Examplebackup\pcores/my_timer.prj

already exists, will be overwrite and removed afterward ...

INFO:EDK:948 - Create temparary xst project file:

D:\thobmei\Examplebackup\pcores/my_timer.prj

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

proc_common_pkg.vhd" in Library proc_common_v3_00_a.

Package <proc_common_pkg> compiled.

Package body <proc_common_pkg> compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

or_muxcy.vhd" in Library proc_common_v3_00_a.

Entity <or_muxcy> compiled.

Entity <or_muxcy> (Architecture <implementation>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

family_support.vhd" in Library proc_common_v3_00_a.

Package <family_support> compiled.

Package body <family_support> compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

counter_f.vhd" in Library proc_common_v3_00_a.

Entity <counter_f> compiled.

Entity <counter_f> (Architecture <imp>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

pselect_f.vhd" in Library proc_common_v3_00_a.

Entity <pselect_f> compiled.

Entity <pselect_f> (Architecture <imp>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

or_gate128.vhd" in Library proc_common_v3_00_a.

Entity <or_gate128> compiled.

Entity <or_gate128> (Architecture <imp>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

ipif_pkg.vhd" in Library proc_common_v3_00_a.

Package <ipif_pkg> compiled.

Package body <ipif_pkg> compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/h

dl/vhdl/plb_address_decoder.vhd" in Library plbv46_slave_single_v1_01_a.

Entity <plb_address_decoder> compiled.

Entity <plb_address_decoder> (Architecture <IMP>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/h

dl/vhdl/plb_slave_attachment.vhd" in Library plbv46_slave_single_v1_01_a.

Entity <plb_slave_attachment> compiled.

Entity <plb_slave_attachment> (Architecture <implementation>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl

/vhdl/interrupt_control.vhd" in Library interrupt_control_v2_01_a.

Entity <interrupt_control> compiled.

Entity <interrupt_control> (Architecture <implementation>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/h

dl/vhdl/plbv46_slave_single.vhd" in Library plbv46_slave_single_v1_01_a.

Entity <plbv46_slave_single> compiled.

Entity <plbv46_slave_single> (Architecture <implementation>) compiled.

Compiling vhdl file

"D:/thobmei/Examplebackup/pcores/my_timer_v1_00_a/hdl/vhdl/my_timer.vhd" in

Library my_timer_v1_01_a.

ERROR:HDLParsers:3317 -

"D:/thobmei/Examplebackup/pcores/my_timer_v1_00_a/hdl/vhdl/my_timer.vhd" Line

75. Library my_timer_v1_00_a cannot be found.

ERROR:HDLParsers:3014 -

"D:/thobmei/Examplebackup/pcores/my_timer_v1_00_a/hdl/vhdl/my_timer.vhd" Line

76. Library unit my_timer_v1_00_a is not available in library

my_timer_v1_01_a.

ERROR:EDK:2121 - Parse Errors encountered in HDL source

WARNING:EDK:2579 - Unable to delete temparary project file

D:\thobmei\Examplebackup\pcores\my_timer.prj : 13

Parsing PAO project file successfully ...

Analyzing HDL source files ...

Analyzing HDL source files successfully ...

HDL language for the peripheral (top level) design unit my_timer is vhdl ...

WARNING:EDK:2221 - Project file D:\thobmei\Examplebackup\pcores/my_timer.prj

already exists, will be overwrite and removed afterward ...

INFO:EDK:948 - Create temparary xst project file:

D:\thobmei\Examplebackup\pcores/my_timer.prj

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

proc_common_pkg.vhd" in Library proc_common_v3_00_a.

Package <proc_common_pkg> compiled.

Package body <proc_common_pkg> compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

or_muxcy.vhd" in Library proc_common_v3_00_a.

Entity <or_muxcy> compiled.

Entity <or_muxcy> (Architecture <implementation>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

family_support.vhd" in Library proc_common_v3_00_a.

Package <family_support> compiled.

Package body <family_support> compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

counter_f.vhd" in Library proc_common_v3_00_a.

Entity <counter_f> compiled.

Entity <counter_f> (Architecture <imp>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

pselect_f.vhd" in Library proc_common_v3_00_a.

Entity <pselect_f> compiled.

Entity <pselect_f> (Architecture <imp>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

or_gate128.vhd" in Library proc_common_v3_00_a.

Entity <or_gate128> compiled.

Entity <or_gate128> (Architecture <imp>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

ipif_pkg.vhd" in Library proc_common_v3_00_a.

Package <ipif_pkg> compiled.

Package body <ipif_pkg> compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/h

dl/vhdl/plb_address_decoder.vhd" in Library plbv46_slave_single_v1_01_a.

Entity <plb_address_decoder> compiled.

Entity <plb_address_decoder> (Architecture <IMP>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/h

dl/vhdl/plb_slave_attachment.vhd" in Library plbv46_slave_single_v1_01_a.

Entity <plb_slave_attachment> compiled.

Entity <plb_slave_attachment> (Architecture <implementation>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl

/vhdl/interrupt_control.vhd" in Library interrupt_control_v2_01_a.

Entity <interrupt_control> compiled.

Entity <interrupt_control> (Architecture <implementation>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/h

dl/vhdl/plbv46_slave_single.vhd" in Library plbv46_slave_single_v1_01_a.

Entity <plbv46_slave_single> compiled.

Entity <plbv46_slave_single> (Architecture <implementation>) compiled.

Compiling vhdl file

"D:/thobmei/Examplebackup/pcores/my_timer_v1_00_a/hdl/vhdl/user_logic.vhd" in

Library my_timer_v1_00_a.

Entity <user_logic> compiled.

Entity <user_logic> (Architecture <IMP>) compiled.

Compiling vhdl file

"D:/thobmei/Examplebackup/pcores/my_timer_v1_00_a/hdl/vhdl/my_timer.vhd" in

Library my_timer_v1_00_a.

Entity <my_timer> compiled.

Entity <my_timer> (Architecture <IMP>) compiled.

Analyzing HDL attributes ...

Entity name = my_timer

INFO:EDK:1607 - IPTYPE set to value : PERIPHERAL

INFO:EDK:1511 - IMP_NETLIST set to value : TRUE

INFO:EDK:1486 - HDL set to value : VHDL

WARNING:EDK:2579 - Unable to delete temparary project file

D:\thobmei\Examplebackup\pcores\my_timer.prj : 13

HDL language for the peripheral (top level) design unit my_timer is vhdl ...

WARNING:EDK:2221 - Project file D:\thobmei\Examplebackup\pcores/my_timer.prj

already exists, will be overwrite and removed afterward ...

INFO:EDK:948 - Create temparary xst project file:

D:\thobmei\Examplebackup\pcores/my_timer.prj

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

proc_common_pkg.vhd" in Library proc_common_v3_00_a.

Package <proc_common_pkg> compiled.

Package body <proc_common_pkg> compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

or_muxcy.vhd" in Library proc_common_v3_00_a.

Entity <or_muxcy> compiled.

Entity <or_muxcy> (Architecture <implementation>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

family_support.vhd" in Library proc_common_v3_00_a.

Package <family_support> compiled.

Package body <family_support> compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

counter_f.vhd" in Library proc_common_v3_00_a.

Entity <counter_f> compiled.

Entity <counter_f> (Architecture <imp>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

pselect_f.vhd" in Library proc_common_v3_00_a.

Entity <pselect_f> compiled.

Entity <pselect_f> (Architecture <imp>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

or_gate128.vhd" in Library proc_common_v3_00_a.

Entity <or_gate128> compiled.

Entity <or_gate128> (Architecture <imp>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/

ipif_pkg.vhd" in Library proc_common_v3_00_a.

Package <ipif_pkg> compiled.

Package body <ipif_pkg> compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/h

dl/vhdl/plb_address_decoder.vhd" in Library plbv46_slave_single_v1_01_a.

Entity <plb_address_decoder> compiled.

Entity <plb_address_decoder> (Architecture <IMP>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/h

dl/vhdl/plb_slave_attachment.vhd" in Library plbv46_slave_single_v1_01_a.

Entity <plb_slave_attachment> compiled.

Entity <plb_slave_attachment> (Architecture <implementation>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl

/vhdl/interrupt_control.vhd" in Library interrupt_control_v2_01_a.

Entity <interrupt_control> compiled.

Entity <interrupt_control> (Architecture <implementation>) compiled.

Compiling vhdl file

"C:/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/h

dl/vhdl/plbv46_slave_single.vhd" in Library plbv46_slave_single_v1_01_a.

Entity <plbv46_slave_single> compiled.

Entity <plbv46_slave_single> (Architecture <implementation>) compiled.

Compiling vhdl file

"D:/thobmei/Examplebackup/pcores/my_timer_v1_00_a/hdl/vhdl/my_timer.vhd" in

Library my_timer_v1_01_a.

ERROR:HDLParsers:3317 -

"D:/thobmei/Examplebackup/pcores/my_timer_v1_00_a/hdl/vhdl/my_timer.vhd" Line

75. Library my_timer_v1_00_a cannot be found.

ERROR:HDLParsers:3014 -

"D:/thobmei/Examplebackup/pcores/my_timer_v1_00_a/hdl/vhdl/my_timer.vhd" Line

76. Library unit my_timer_v1_00_a is not available in library

my_timer_v1_01_a.

ERROR:EDK:2121 - Parse Errors encountered in HDL source

WARNING:EDK:2579 - Unable to delete temparary project file

D:\thobmei\Examplebackup\pcores\my_timer.prj : 13

 

 

 

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Xilinx Employee
Xilinx Employee
12,642 Views
Registered: ‎11-28-2007

Re: Import Peripheral in XPS

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No problem! Making mistakes is only human.

Do try to carefully read error messages or warnings. They don't always tell the truth, but they can lead to the root cause and a solution.

 

 

Best regards,

Dries

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Observer thobmei
Observer
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Registered: ‎05-28-2010

Re: Import Periferal in XPS

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have I 2 modifie the core file? when yes how?

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Xilinx Employee
Xilinx Employee
10,105 Views
Registered: ‎08-01-2007

Re: Import Periferal in XPS

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it looks there is problem in your custom ip source code, you can use ISE to check the synax first.

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Observer thobmei
Observer
10,097 Views
Registered: ‎05-28-2010

Re: Import Periferal in XPS

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Ive already checked the source Code ... No Errors.

I have the Same Problem when I try the XPS generated Template without any changes ...

 

I also tried using a new XPS Project ...  without successes

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Xilinx Employee
Xilinx Employee
10,089 Views
Registered: ‎11-28-2007

Re: Import Periferal in XPS

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Hi Tobias,

 

when you have errors, it's import to carefully read the message, try to understand it and solve the root cause.

In this case, I see:

 

Compiling vhdl file "D:/thobmei/Examplebackup/pcores/my_timer_v1_00_a/hdl/vhdl/my_timer.vhd" in Library my_timer_v1_01_a.
ERROR:HDLParsers:3317 - "D:/thobmei/Examplebackup/pcores/my_timer_v1_00_a/hdl/vhdl/my_timer.vhd" Line 75. Library my_timer_v1_00_a cannot be found.

It compiles the VHDL file in the library "my_timer_v1_01_a", but in the code library "my_timer_v1_00_a" is specified.

 

 

Solution is either to correct the VHDL code and refer to the library "my_timer_v1_01_a".

Or either correct the libraries to "my_timer_v1_00_a" in which the VHDL files are compiled:

- either via the PAO file which you read in

- either manually in the GUI where you specify the VHDL files/libraries.

 

Of course, do not apply both solutions (both VHDL + compile libraries) because then you have the same problem :smileyhappy:

 

 

Best regards,

Dries

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Observer thobmei
Observer
10,067 Views
Registered: ‎05-28-2010

Re: Import Peripheral in XPS

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Thx   Ill give it a try...

 

I thought the library should be changed automatically ...

by the import Wizard..

 

As far a Ive seen it no Xapp tells me about changing things like the library ...

 

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Xilinx Employee
Xilinx Employee
10,058 Views
Registered: ‎08-01-2007

Re: Import Peripheral in XPS

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you can refer to xapp967 about creating and importing peripheral.

And when you are trying to import the design, are you select the pao file?

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Observer thobmei
Observer
10,032 Views
Registered: ‎05-28-2010

Re: Import Peripheral in XPS

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hard way ... but now i think I got it ....

finaly it looks like Id been to stupid 2 read ...

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Xilinx Employee
Xilinx Employee
12,643 Views
Registered: ‎11-28-2007

Re: Import Peripheral in XPS

Jump to solution

No problem! Making mistakes is only human.

Do try to carefully read error messages or warnings. They don't always tell the truth, but they can lead to the root cause and a solution.

 

 

Best regards,

Dries

--------------------------------------------------------------------------------------------------------------------
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