12-22-2008 02:39 PM
I'm using EDK 10.1, specced for the ML501. When I reach the mapping phase, I get the following error (several times):
ERROR:PhysDesignRules:1492 - Incompatible programming for comp mb_plb_M_ABus<1>.
The pair of luts SLICEL_A5LUT and SLICEL_A6LUT must have a compatible
equation, lower bits must be programmed the same. The SLICEL_A5LUT hex
equation is <O5=0x08080808> and the SLICEL_A6LUT hex equation is
My system is fairly standard. I used BSB and added a few things (LEDs,switches), but nothing particularly exotic. Is there something obvious that I might have missed, or is this likely to be an error with DRC?
12-25-2008 11:22 PM
I tried the same BSB design including all the default peripherals. I was unable to see that error.
Can you try clean up all the project files (Project==> Clean all generated files) in XPS GUI?
Also try to run the design in the latest service pack.
02-27-2009 01:25 AM - edited 02-27-2009 01:37 AM
I am using all Xilinx products of version 10.1.03 and i am kind of dealing with the same problem. I am trying to use microblaze processor in my ml507, I have only added a UART module, and the rest is autofilled, i mean the busses and so on. I have also modified my .ucf file for Tx, Rx, CLK and RST. But the error mgs i get is:
ERROR:PhysDesignRules:1492 - Incompatible programming for comp
mb_plb_M_ABus<29,25,21,17,13,9,5,1>. The pair of luts SLICEL_(A,B,C,D)5LUT and SLICEL_(A,B,C,D)6LUT must have a
compatible equation, lower bits must be programmed the same. The SLICEL_(A,B,C,D)5LUT
hex equation is <O5=0x08080808> and the SLICEL_(A,B,C,D)6LUT hex equation is
Namely, for each <> entry from 1 to 29, every () entry from A do D the error occurs. As a total of 32 errors outcome.
29 | A, B, C, D
25 | A, B, C, D
5 | A, B, C, D
1 | A, B, C, D
If i was able to explain the msg, do you have any advice how to solve this?
i am using plb as a shared bus, but on the contrary, when i use it as a 1master1slave mode, i get an error msg as:
ERROR:MDT ...\system.mhs C_P2P parameter is set to 1 in MHS, when there are more than 1 master(s) / slave(s) on the bus.
Just stuck in here, plz help, thank you vm.