06-07-2011 11:20 AM
Xilinx Virtex-6 ML605
with FMC Connector breakout board FMC-105-DEBUG
EDK Version 13.1 – Linux
I am currently working on a project where I need to tap into the SDA and SCL signals of the IIC bus to determine specific timing information. I would like to output both of those signals to some pin on the FMC. However, due to the tri-state nature of these signals, I have not been successful.
I have attempted to create a project in XPS that outputs these signals by creating a SCL_in, SDA_in, SCL_out, and SDA_out signals in a new module. I then connected the 'in' signals to the IIC_EEPROM_SDA and IIC_EEPROM_SCL ports defined in the top-level system.mhs file. This resulted in the error that “IIC_EEPROM_SDA is not driven,” and the same for the SCL.
Then, I tried just to declare the port as an inout, as is done in the MPD file for the AXI_IIC module. This resulted in the error of having multiple drivers.
As an experiment, I created a very simple module in ISE containing an nested inout port. The code is posted below.
assign nested_inout = nested_oe ? nested_sigin : 1'bz;
assign inout_tap = signal_inout;
nested_iomodule nest1( signal_inout, output_enable, signal_in );
When I synthesized and ran this code, it worked correctly; that is, the wire inout_tap correctly reflected the state of the tri-state buffer (it was a hard 0 when the tri-state was near a 0, and was a hard 1 when the tri-state was near a 1).
I would like to do the same thing in XPS, but for the SCL and SDA wires present. If anyone has any tips, they will be greatly appreciated. Thank you.
06-07-2011 01:46 PM
I ran into a similar problem a while back.
The solution I found is to create a signal for these signals inside of XPS. Do not 'Connect to external pins"
Once this is done, edit your .mhs file looking for these signal names. They will be buried in the file inside the IIC block.
You need to route them out of the .mhs file by connecting them to external signals at the top of the .mhs file.
Doing this forces the XPS tool to not place iodrivers on these signals. It is assuming you are going to use them for other logic inside the fpga. Rerun the netlist builder to update all the files.
Once this is done, go inside the system_stub.vhd (or equivalent) and route them as you would normal signals.
This is assuming you microblaze system is a component in your top level vhdl file.
08-29-2017 09:37 PM
Did you complete this I2c verification successfully with FMC-105-Debug connector?
If yes, please help me the pin connection of AArdvark i2c/spi host adapter with ML605 board.