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ragnarok2000
Visitor
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Registered: ‎04-14-2011

Integration of EDK into ISE; Problems with timing constraints; keep hierarchy

Hi,

 

I try to do partial reconfiguration with a microblace and hwicap on a ml506 (virtex5).

I build a system with EDK and imported it to an ISE project (as a sub module).

Then I follow the flow using Planahead (ug702).

 

As stated in the hwicap documentation I try to use following timing constraints:

NET "clk_125_0000MHzPLL0" TNM = "PLBCLK_GRP";
NET "clk_100_0000MHz" TNM = "ICAPCLK_GRP";
TIMESPEC TS_TIG0 = FROM "PLBCLK_GRP" TO "ICAPCLK_GRP" TIG;
TIMESPEC TS_TIG1 = FROM "ICAPCLK_GRP" TO "PLBCLK_GRP" TIG;
##The following MAXDELAY constraints are required in the UCF:
NET "system_i/xps_hwicap_0/xps_hwicap_0/HWICAP_CTRL_I/icap_statemachine_I1/Icap_datain<*>" MAXDELAY = 2 ns;
NET "system_i/xps_hwicap_0/xps_hwicap_0/HWICAP_CTRL_I/icap_statemachine_I1/Icap_ce" MAXDELAY = 2 ns;
NET "system_i/xps_hwicap_0/xps_hwicap_0/HWICAP_CTRL_I/icap_statemachine_I1/Icap_we" MAXDELAY = 2 ns;

 

But then I get errors:

CRITICAL WARNING: [Constraints-11] Could not find net 'system_i/xps_hwicap_0/xps_hwicap_0/HWICAP_CTRL_I/icap_statemachine_I1/Icap_datain<*>' [/scratch/dmuench/dprsysv5/PLANAHED/proj/proj.srcs/constrs_1/imports/dprsysv5/ISE/top.ucf:25]
CRITICAL WARNING: [Constraints-10] Could not create constraint 'MAXDELAY' [/scratch/dmuench/dprsysv5/PLANAHED/proj/proj.srcs/constrs_1/imports/dprsysv5/ISE/top.ucf:25]
CRITICAL WARNING: [Constraints-11] Could not find net 'system_i/xps_hwicap_0/xps_hwicap_0/HWICAP_CTRL_I/icap_statemachine_I1/Icap_ce' [/scratch/dmuench/dprsysv5/PLANAHED/proj/proj.srcs/constrs_1/imports/dprsysv5/ISE/top.ucf:26]
CRITICAL WARNING: [Constraints-10] Could not create constraint 'MAXDELAY' [/scratch/dmuench/dprsysv5/PLANAHED/proj/proj.srcs/constrs_1/imports/dprsysv5/ISE/top.ucf:26]
CRITICAL WARNING: [Constraints-11] Could not find net 'system_i/xps_hwicap_0/xps_hwicap_0/HWICAP_CTRL_I/icap_statemachine_I1/Icap_we' [/scratch/dmuench/dprsysv5/PLANAHED/proj/proj.srcs/constrs_1/imports/dprsysv5/ISE/top.ucf:27]
CRITICAL WARNING: [Constraints-10] Could not create constraint 'MAXDELAY' [/scratch/dmuench/dprsysv5/PLANAHED/proj/proj.srcs/constrs_1/imports/dprsysv5/ISE/top.ucf:27]

 

I have checked the paths. They are using the correct chain of instances. I have tried to synthesize the static logic with "keep hierarchy=yes" but I think the problem lies in edk. I think ISE uses only the generated netlists by edk. I think the IP cores in EDK are not synthesized/generated with the propertity "keep hierarchy=yes"?

 

Has someone an idea to solve this problem?

 

Best regards

ragnar

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golson
Scholar
Scholar
2,003 Views
Registered: ‎04-07-2008

Try changing net constraint

from

NET "system/....

to

NET "*/system/...

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