cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
3,961 Views
Registered: ‎04-15-2009

Interfacing external memory to custop IP user logic of EDK

Hi all i want to design a custom IP  which sends addr, data and controls to read and write a SRAM  which is external to FPGA.

I have brought out addr data and contols outside FPGA and connected it to SRAM..

I have Register space for register read and write  and the rest of 8 address ranges alloted for SRAM..

 

When i compile my design i am not able to access Rester space also,though there are no errors.

 

Without the SRAM logic i am able to access Rgister space as well as the  8 address ranges..Please suggest me regarding this

Thankyou.

0 Kudos
3 Replies
Highlighted
Explorer
Explorer
3,959 Views
Registered: ‎12-29-2008

I better suggest is connect chipscope and see whether what ever you are driving is going properly on to the signals..

hope it may help because problem may be in your custom ip which may not be generating proper timing to SRAM.

 

regards,

Krishna Kishore 

0 Kudos
Highlighted
Observer
Observer
3,906 Views
Registered: ‎10-30-2008

I have the silimar problem. Could you please give me some adivce? How did you connect your IP with SRAM? By MCH bus?

 

Many thanks.

0 Kudos
Highlighted
3,880 Views
Registered: ‎04-15-2009

Hello all, i found what is the problem but i donot have the solution..The problem is one cannot drive the signal Bus2IP_RNW outside..I also tried to register it withe Bus2IP_CLK and then assign it to putput. But still it was of no use. Asoon as i drive that signal out side., i cannot access it..If cnyone any point out wat may be the other way please do lemme know..

Thank u

0 Kudos