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Voyager
Voyager
171 Views
Registered: ‎02-01-2013

Is there a way to lengthen the time-out setting for XSDB/XSCT?

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Hullo World,

I've got a single board containing a Zynq MPSoC along with an A7. There's a Chip2Chip (single-lane, Aurora 8B10B) link between them.

I'm trying to show that the C2C link is working, before I hand the board off to software.

I'm using XSCT to invoke a memory read command at the Zynq (PSU/A53_0) to fetch a value from a register on the A7. I've got everything instrumented up, and I can follow the read from the PSU, through an AXI Interconnect, into the Zynq C2C, out of the A7 C2C, through another AXI Interconnect, to the little IP that holds the register being read. The correct read value is (eventually) returned all the way to the PSU--based on the ILA trace.

However, my XSCT command "mrd -force 0xaddress 1" fails and returns "Memory read error at 0xaddress. EDITR overrun ". Since the Zynq-side transaction takes ~140 clock cycles to complete, I assume XSCT is bailing-out before the transaction finishes due to some time-out mechanism. 

Is there a way to lengthen this time-out?

-Joe G.

 

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Voyager
Voyager
75 Views
Registered: ‎02-01-2013

Re: Is there a way to lengthen the time-out setting for XSDB/XSCT?

Jump to solution

 

My lab partner Mr. Slaw decided to help out on this... We call him 'Murphy'.

So we added an AXI Protocol Analyzer to the interface between the Zynq MPSoC and the first AXI Interconnect.  We also added a JTAG-to-AXI IP, so that we would be able to create AXI transactions without using the PSU, if needed.

And... the problem went away. If we use XSDB/XSCT to do a read over the Chip2Chip interface, there's no more error. Needless to say, the Protocol Analyzer never fires. We can even perform reads over the Chip2Chip using U-boot commands without a problem.

Don't know what happened. I blame Murphy.

Thank you for the help.

-Joe G.

 

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2 Replies
Xilinx Employee
Xilinx Employee
95 Views
Registered: ‎10-21-2010

Re: Is there a way to lengthen the time-out setting for XSDB/XSCT?

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Hi @jg_bds,

The timeout is hardcoded to 100msec, which is much higher than 140 cycles. The problem you are seeing is not related to timeout. The error is returned by the A53 core itself. It means that there is an overlflow of instruction FIFO in the A53 core. However, its not clear when this happens. Can you try the following

1. Access the memory from PSU target instead of A72 core

2. Lower the Jtag frequency to something like 100KHz

3. Use AXI protocol checker to see if there are any AXI errors

Voyager
Voyager
76 Views
Registered: ‎02-01-2013

Re: Is there a way to lengthen the time-out setting for XSDB/XSCT?

Jump to solution

 

My lab partner Mr. Slaw decided to help out on this... We call him 'Murphy'.

So we added an AXI Protocol Analyzer to the interface between the Zynq MPSoC and the first AXI Interconnect.  We also added a JTAG-to-AXI IP, so that we would be able to create AXI transactions without using the PSU, if needed.

And... the problem went away. If we use XSDB/XSCT to do a read over the Chip2Chip interface, there's no more error. Needless to say, the Protocol Analyzer never fires. We can even perform reads over the Chip2Chip using U-boot commands without a problem.

Don't know what happened. I blame Murphy.

Thank you for the help.

-Joe G.

 

0 Kudos