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lauziepi
Adventurer
Adventurer
11,660 Views
Registered: ‎04-06-2012

JTAG boundary scan from a FPGA

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Hi,

 

my plan is to use four GPIO pins of a FPGA to create a JTAG chain with another FPGA. On the first FPGA I have a microblaze, and I'd like to be able to perform a boundary scan to read the second FPGA's id. What would be the easiest way to achieve this? I'm pretty sure there should be ab open-source JTAG API somewhere but I could not find anything.

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gszakacs
Professor
Professor
21,997 Views
Registered: ‎08-14-2007

If you want to use the MicroBlaze to bit-bang the JTAG interface over GPIO, you probably want to look at XAPP058.

 

Document:

http://www.xilinx.com/support/documentation/application_notes/xapp058.pdf

 

Design files:

http://www.xilinx.com/support/documentation/application_notes/xapp058.zip

 

 

-- Gabor

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austin
Scholar
Scholar
11,656 Views
Registered: ‎02-27-2008

l,

 

Search for;

 

jtag tap controller verilog or vhdl code.

 

They are out there.

 

Just need to know what the name ofthe function is you need (JTAG test access port - tap-  controller).

Austin Lesea
Principal Engineer
Xilinx San Jose
gszakacs
Professor
Professor
21,998 Views
Registered: ‎08-14-2007

If you want to use the MicroBlaze to bit-bang the JTAG interface over GPIO, you probably want to look at XAPP058.

 

Document:

http://www.xilinx.com/support/documentation/application_notes/xapp058.pdf

 

Design files:

http://www.xilinx.com/support/documentation/application_notes/xapp058.zip

 

 

-- Gabor

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