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7,331 Views
Registered: ‎08-14-2009

Join several BRAMs to create the lager memory block

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Hi all

I'm developing a project on ML605 board with EDK and SDK, using BRAM to store code but not enough. I have added more BRAM and total memory lager than necessary, generate bit file successfully but generate linker script not success. I want to ask you is there any way to join these BRAMs to as one lager memory block. Thanks.

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9,264 Views
Registered: ‎08-14-2009

Re: Join several BRAMs to create the lager memory block

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I have tried to compile with EDK successful. I also followed AR#16536, solution 3 (http://www.xilinx.com/support/answers/16536.htm), it was ok.

Thank you very much.

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8 Replies
Xilinx Employee
Xilinx Employee
7,303 Views
Registered: ‎12-17-2007

Re: Join several BRAMs to create the lager memory block

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I am going to move this over to the EDK forum for you so that they can give you some guidance.

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Scholar golson
Scholar
7,275 Views
Registered: ‎04-07-2008

Re: Join several BRAMs to create the lager memory block

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You should be able to increase the size of the BRAM in the system assembly view.  I do this all the time there.

select the bram and click on it where it displays the size it should allow you to increase the size there.

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Xilinx Employee
Xilinx Employee
7,260 Views
Registered: ‎08-02-2007

Re: Join several BRAMs to create the lager memory block

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Hi,

 

1, Check the number of BRAM's available in the design.

 

2, You can either change the address range in the address tab of an existing memory instance

 

or

 

Add xps_bram_if_cntlr along with a bram block to include more memory.

 

or

 

Generate a coregen based memory block, import it into the edk design.

 

Thnx

 

 

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7,259 Views
Registered: ‎08-14-2009

Re: Join several BRAMs to create the lager memory block

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Hi Golson,

Thank you for your reply. Microblaze on Virtex-6 is only supported maximum 256Kb/1BRAM, my application code is 312Kb. So I added additional one BRAM 256Kb, 2 BRAMs have address range continuous, but when compile application, the following error appear:

 

ERROR:EDK:3165 - elfcheck failed!
The following sections did not fit into Processor  memory:
Section .bss (0x28300 - 0xC023B)

 

ERROR:EDK:3165 - elfcheck failed!The following sections did not fit into Processor  memory: Section .bss (0x28300 - 0xC023B).

Can you give me any guidances?

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Xilinx Employee
Xilinx Employee
7,256 Views
Registered: ‎08-02-2007

Re: Join several BRAMs to create the lager memory block

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Hi,

 

There have been some issues seen with SDK. Please try to compile with EDK .

 

Thnx

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Highlighted
9,265 Views
Registered: ‎08-14-2009

Re: Join several BRAMs to create the lager memory block

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I have tried to compile with EDK successful. I also followed AR#16536, solution 3 (http://www.xilinx.com/support/answers/16536.htm), it was ok.

Thank you very much.

View solution in original post

Explorer
Explorer
6,877 Views
Registered: ‎05-30-2008

Re: Join several BRAMs to create the lager memory block

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I have the same problem. Since software designs must be built in SDK in 12.2 I am afraid to upgrade to 12.2. Or will this be in 13.0?

 

When does Xilinx plan to fix the issues seen with SDK? Hopefully before they make it mandatory!

 

Please let me know if SDK is require for building software in v12.2.

 

Thank you,

Josh

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Explorer
Explorer
6,874 Views
Registered: ‎05-30-2008

Re: Join several BRAMs to create the lager memory block

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@hem_8030 wrote:

Hi,

 

There have been some issues seen with SDK. Please try to compile with EDK .

 

Thnx


 

EDK does not work for me either!

 

Ah wait - it does, but you have to trick it.

 

in the linker script:

 

 

MEMORY
{
   ilmb_cntlr_dlmb_cntlr : ORIGIN = 0x00000050, LENGTH = 0x0000FFB0
   xps_BRAM_cntlr_0 : ORIGIN = 0x10000000, LENGTH = 0x00010000
   xps_BRAM_cntlr_1 : ORIGIN = 0x10010000, LENGTH = 0x00010000
xps_BRAM_cntlr_both : ORIGIN = 0x10000000, LENGTH = 0x00020000
   MPMC_LPDDR_C_MPMC_BASEADDR : ORIGIN = 0x48000000, LENGTH = 0x08000000
}

 

MEMORY{  

ilmb_cntlr_dlmb_cntlr : ORIGIN = 0x00000050, LENGTH = 0x0000FFB0  

xps_BRAM_cntlr_0 : ORIGIN = 0x10000000, LENGTH = 0x00010000  

xps_BRAM_cntlr_1 : ORIGIN = 0x10010000, LENGTH = 0x00010000

  xps_BRAM_cntlr_both : ORIGIN = 0x10000000, LENGTH = 0x00020000  

MPMC_LPDDR_C_MPMC_BASEADDR : ORIGIN = 0x48000000, LENGTH = 0x08000000

}

 

I then used xps_BRAM_cntlr_both as my location for .text (my large section that would not fit).

 

It works!

 

I tried the exact same thing in SDK and it generates an elf file. This elf file is then checked and it fails the check ("elfcheck failed").

 

Is this elf file still valid? Is it the same as the one in EDK except EDK lets it slide past the check? Could I just use the elf file generated by SDK even though it fails?

 

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