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masheeen
Participant
Participant
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Registered: ‎05-22-2018

Load A53 Application/OS after FSBL has completed boot

I hope I am able to explain this clearly, so it makes sense.

Running Zynq Ultrascale+.

We are trying to boot from an FSBL (on R5) a set of partitions, including. PMUFW, bitstream, Arm Trusted Firmware(ATF), and an R5 application that will act as a platform support. The R5 application will be the last partition loaded from the FSBL. After the rest of the system comes up, we want to use that R5 application to get the A53 (APU) side to load our OS. The reason to wait on booting the OS is boot time and other requirements.

The issue coming up is the inability, right now, to determine how to put the A53 back into reset and move its program counter to the location in DDR where the OS resides. The A53 is already running, because of the ATF having been loaded from the FSBL. Is this something that would need to change? Would it be possible to load the ATF and then the OS on the A53 after the FSBL completes loading all partitions? Can the A53 be put into reset and move the PC to get the OS to boot, without losing the ATF? Is there a way to set the exception level outside of the boot.bif/bin files for the FSBL to establish, as the OS will need EL-1.

Any advice to point me into a more appropriate direction with this is greatly appreciated.

 

Thanks.

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jimmimarquart
Observer
Observer
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Registered: ‎12-11-2018

Hi,

Did you find a solution for this?
I am using uboot to load applications for A53 cpu0 and cpu1 into DDR RAM, and I can launch cpu0 from uboot.
cpu0 is in charge of reset of cpu1, however I cannot manage to change the program counter of cpu1 to the start address in DDR.

Hence basically I need to know what "con -addr <0x address_in_ram>" from the xsdk XSCT does to cpu1, because this seems to change the PC of cpu1.

Kind regards.

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masheeen
Participant
Participant
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Registered: ‎05-22-2018

I've not solved this, as of yet. In my search for answers I've come across the following post that may help for your situation, but I'm not sure.

https://forums.xilinx.com/t5/ACAP-and-SoC-Boot-and/How-to-load-and-launch-an-A53-application-using-R5/m-p/1064979/highlight/false#M4177

With regard to you seeing what goes on behind the scenes for that command in XSCT, have you tried going into debug mode in SDK with your app, then using that command in XSCT and stepping through to see what is happening? That may be able to show you what is going on in the registers to move the PC for APU1, which could allow you to follow the same steps for the other APUs.

Good luck in your search and hopefully we shall find the answers we seek, soon.

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jimmimarquart
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Registered: ‎12-11-2018

hi,

i managed to change the pc while searching the forums.

https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/ZynqMP-start-multiple-cores/m-p/983549

Hence basically you write the start-address in DDR which you specify in your linker-script.ld to these registers.

For instance if your start address is 0x4000000 you type, in your APU0

    Xil_Out32(0xFD5C0048, 0x04000000); //RVBARADDR1L
    Xil_Out32(0xFD5C004C, 0x00000000); //RVBARADDR1H

and then followed by a reboot of APU1, which can be done as:

#define XRESETPS_CRF_APB_BASE     (XPAR_PSU_CRF_APB_S_AXI_BASEADDR) //0xFD1A0000 , from xparameters.h
#define XRESETPS_CRF_APB_RST_FPD_APU ((XRESETPS_CRF_APB_BASE) + ((u32)0X00000104U))
#define ACPU1_PWRON_RESET_MASK    ((u32)0X00000800U)
#define ACPU1_RESET_MASK          ((u32)0X00000002U)

void boot_cpu1() {
    u32 regVal;
    regVal = Xil_In32(XRESETPS_CRF_APB_RST_FPD_APU);
    regVal &= ~(ACPU1_RESET_MASK | ACPU1_PWRON_RESET_MASK);
    Xil_Out32(XRESETPS_CRF_APB_RST_FPD_APU, regVal);
}

At least that worked for me.

I hope this can help in your situation.

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masheeen
Participant
Participant
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Registered: ‎05-22-2018

Thanks so much for the information. It helped get some forward motion to a resolution for me, however I'm still unable to reset APU0. I modified what you sent to focus on APU0, but with the ATF already running, I'm still not having luck getting the core to reset after setting the DDR address as the start address.

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jimmimarquart
Observer
Observer
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Registered: ‎12-11-2018

Hi,
For APU0 i think you need to do a soft-reset. I am not sure the following snippet is fully funcitionel.
You can find more information in the register reference  

Look for CRL_APB Module, RESET_CTRL and RESET_REASON.

//// from xresetps_hw.h
/* CRL_APB defines */
#define XRESETPS_CRL_APB_BASE     (XPAR_PSU_CRL_APB_S_AXI_BASEADDR)
/* RESET_CTRL Address and mask definations */
#define XRESETPS_CRL_APB_RESET_CTRL ((XRESETPS_CRL_APB_BASE) + ((u32)0X00000218U))
#define SOFT_RESET_MASK           ((u32)0X00000010U)

void soft_reset() {
    regVal = Xil_In32(XRESETPS_CRL_APB_RESET_CTRL);
    Xil_Out32(XRESETPS_CRL_APB_RESET_CTRL, (regVal | SOFT_RESET_MASK));
}

 

Good luck

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