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Scholar
Scholar
9,925 Views
Registered: ‎04-07-2008

Lwip Delay between TCP Packets

Hi,

  I am trying to figure out if I can increase my TCP bandwidth.  Using a PC timer I see that as I send TCP Packets that the delay is in the range of 500 us on average.

There may be a couple at the start with much less delay between TCP Packets.  But most of the packets after the first few are in the same range.

 

Does any one know what the LWIP Delayed Acknowledge timer is set to.  I have been looking on the web in general for a solution to this.  I program my PC in Visual C++

using Winsock so I am going to see if using  TCP NO DELAY will have a positive change.  Since this will cause the Nagle Algorithm to be disabled and packets are

supposed to be sent immediately rather waiting for a delayed acknowledge to come first.

Thank You,

  Gary

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Scholar
Scholar
9,905 Views
Registered: ‎04-07-2008

The TCP_NODELAY option did not help. So I looked with WireShark and I can see that Each Acknowledge occurs after 500 us after the packet was sent.  I am

wondering if the Acknowledge delay can be changed or if it takes that long to process my 4040 byte packet.

 

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Scholar
Scholar
9,883 Views
Registered: ‎04-07-2008

I find this curious that the tcp_fast_tmr is set for 250 milliseconds and the slow timer is set to go 500 milliseconds.( in the TCP.h file.

 

And my PC timer says that the delay between packets is 500 us.  I am trying to get my Gigabit ethernet to work.

 

and 16.5 Milliseconds is the setting for the Timer to carry out in the timer functions on the Xilinx board I see.  maybe I really have 16.5 microseconds for this setting.

Message Edited by golson on 09-30-2008 03:27 PM
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Scholar
Scholar
9,865 Views
Registered: ‎04-07-2008

Improved some when I placed in my software settings to offload checksum generation on RX and TX.

This improved my bandwidth around 20 %.  I had the hardware already set up but did not notice the software settings.

 

Still trying to double my bandwidth somehow.

 

 

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Xilinx Employee
Xilinx Employee
9,858 Views
Registered: ‎01-18-2008

To figure out what performance you are achieving vs what is the max possible, it would be helpful if you post info like:

 

Processor, frequency

DMA used?

Packet Size

 

and the Mbps number you are seeing.

 

You could then compare with the numbers available in XAPP1026 or in the lwIP documentation, and see where you stand.

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Scholar
Scholar
9,845 Views
Registered: ‎04-07-2008

Hi vsiva,

 

  I am using the ML505 board and GigE PC Card set up to run at 1000 Mbps.  I increased my packet size to 4040 (DATA) Bytes  (4056 Total Packet Size?).  I have now added

RX and TX checksum offloading.  I am seeing about 400 us between each packet being sent.  I am calculating I think about 60 Megabits per second.

I am using Central DMA to put the data into a IPIF FIFO Transmitter (using the Central DMA).   Processor 100 MHz, PLB 125 MHz. 

Running out of the DDR SDRAM.  RAW Mode.

 

Thank You,

  Gary Olson

Message Edited by golson on 10-02-2008 04:02 AM
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Xilinx Employee
Xilinx Employee
9,831 Views
Registered: ‎01-18-2008

On the ML505, I've seen between 90 - 125 Mbps (for 1500 byte packets).

 

In MicroBlaze, make sure you've enabled barrel shifter and use the max size caches possible. In lwIP settings, make sure your tcp_wnd is set to a reasonable value. So if you are sending 4k packets, you might want to experiment with tcp_wnd settings of 8k-16k. That would mean that your RX/TX FIFO's in xps_ll_temac should also have that much FIFO space.

 

If you are really looking for the last bit of performance, then you can try placing your code sections in SRAM. Note that the data should still reside in DDR for SDMA to work.

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Visitor
Visitor
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Registered: ‎03-25-2009

In the reference design setup(xapp1041)  the processor , ddr2 memory and PLB, all are running at 125 MHz. Is there a way using the same board to speed up the system. e.g. to boost the operating frequency from 125 Mhz to 175 Mhz for all of them?

 

Thanks

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