10-16-2014 02:01 AM
Hello, I'm trying to run MAP to a design and I get the following error.
ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
single OLOGIC component because the site type selected is not compatible.
The component type is determined by the types of logic and the properties and
configuration of the logic it contains. In this case an IO component of type
OLOGIC was chosen because the IO contains symbols and/or properties
consistent with output usage. Please double check that the types of logic
elements and all of their relevant properties and configuration options are
compatible with the physical site type of the constraint.
PAD symbol "dma_fpga_0/PL_CLK" (Pad Signal = PL_CLK)
Signal = dma_fpga_0/dma_fpga_0/USER_LOGIC_I/fpga_spear1/PL_CLK<1>_inv)
Component type involved: OLOGIC
Site Location involved: A20
Site Type involved: IOBM
The device I'm using is a xc5vlx110ff676-2 and the ucf lines reffering to this site are:
NET "PL_CLK" IOSTANDARD = LVCMOS33;
NET "PL_CLK" DRIVE = 24;
NET "PL_CLK" SLEW = FAST;
NET "PL_CLK" LOC = A20;
TIMEGRP ANY = CPUS DSPS FFS HSIOS LATCHES MULTS PADS RAMS BRAMS_PORTA BRAMS_PORTB;
NET "PL_CLK" TNM_NET = "TN_PL_CLK";
TIMESPEC TS_RESET = FROM PADS("PL_CLK") TO "ANY" TIG ;
Any help would be greatly appreciated.
Thank you in advance.
10-17-2014 07:52 AM - edited 10-17-2014 07:53 AM
Can you open technology schematic and show us the connectivity of cells in error?
Do you have any IOB constraints set?
10-21-2014 01:09 AM
Good morning sorry for my late reply.
Do you need the schematic produced by ISE or XPS (my whole design is put together in XPS)?
Watching at my constraints panel in PlanAhead I don't see any IOB constraints. My constraints panel looks like this.
10-21-2014 01:15 AM
I produced a schematic from planAhead. I hope this is what you meant. Signal in question in PL_CLK. Thing is that without the use of a Microblaze, just some stand alone modules synthesized and mapped with ISE and with the same constraints file, the whole thing works just fine and a .bit file can be produced from ISE.
Thanks again for your time.
10-21-2014 01:36 AM
Can you show us where is the net PL_CLK being driven from?
You can open synthesized design, go to Edit --> find. Now search for "nets" with "name" PL_CLK. Right click on the net in "find results" tab and select schematic. Now trace to the inputs of the net and attach the snapshot of same here.
10-21-2014 01:55 AM
Is PL_CLK defined as output port or input port in the design?
If it is defined as output port, it is not possible to drive this to PRE input pin of flops as shown in your second snapshot.
10-21-2014 01:58 AM
PL_CLK as all the PL_CLK vector are defined as shown:
PL_CLK : inout std_logic_vector(3 downto 0);
Also if I synthesize and implement my design with ISE and without the use of partial reconfiguration and a Microblaze processor, everything runs smoothly.