cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
8,459 Views
Registered: ‎10-14-2014

MAP error Pack: 1107

Hello, I'm trying to run MAP to a design and I get the following error.

 

ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
single OLOGIC component because the site type selected is not compatible.

Further explanation:
The component type is determined by the types of logic and the properties and
configuration of the logic it contains. In this case an IO component of type
OLOGIC was chosen because the IO contains symbols and/or properties
consistent with output usage. Please double check that the types of logic
elements and all of their relevant properties and configuration options are
compatible with the physical site type of the constraint.

Summary:
Symbols involved:
PAD symbol "dma_fpga_0/PL_CLK[1]" (Pad Signal = PL_CLK[1])
LUT symbol
"dma_fpga_0/dma_fpga_0/USER_LOGIC_I/fpga_spear1/PL_CLK<1>_inv1_INV_0" (Output
Signal = dma_fpga_0/dma_fpga_0/USER_LOGIC_I/fpga_spear1/PL_CLK<1>_inv)
Component type involved: OLOGIC
Site Location involved: A20
Site Type involved: IOBM

 

The device I'm using is a xc5vlx110ff676-2 and the ucf lines reffering to this site are:


NET "PL_CLK[1]" IOSTANDARD = LVCMOS33;
NET "PL_CLK[1]" DRIVE = 24;
NET "PL_CLK[1]" SLEW = FAST;
NET "PL_CLK[1]" LOC = A20;

TIMEGRP ANY = CPUS DSPS FFS HSIOS LATCHES MULTS PADS RAMS BRAMS_PORTA BRAMS_PORTB;
NET "PL_CLK[1]" TNM_NET = "TN_PL_CLK[1]";
TIMESPEC TS_RESET = FROM PADS("PL_CLK[1]") TO "ANY" TIG ;

 

Any help would be greatly appreciated. 

Thank you in advance.

George.

0 Kudos
7 Replies
Highlighted
Xilinx Employee
Xilinx Employee
8,414 Views
Registered: ‎09-20-2012

Hi,

 

Can you open technology schematic and show us the connectivity of cells in error?

 

Do you have any IOB constraints set?

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
0 Kudos
Highlighted
Visitor
Visitor
8,388 Views
Registered: ‎10-14-2014

Good morning sorry for my late reply.

 

Do you need the schematic produced by ISE or XPS (my whole design is put together in XPS)?

Watching at my constraints panel in PlanAhead I don't see any IOB constraints. My constraints panel looks like this.

 

Untitled.png
0 Kudos
Highlighted
Visitor
Visitor
8,386 Views
Registered: ‎10-14-2014

I produced a schematic from planAhead. I hope this is what you meant. Signal in question in PL_CLK[1]. Thing is that without the use of a Microblaze, just some stand alone modules synthesized and mapped with ISE and with the same constraints file, the whole thing works just fine and a .bit file can be produced from ISE.

 

Thanks again for your time.

Untitled1.png
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
8,378 Views
Registered: ‎09-20-2012

Hi,

 

Can you show us where is the net PL_CLK[1] being driven from?

 

You can open synthesized design, go to Edit --> find. Now search for "nets" with "name" PL_CLK[1]. Right click on the net in "find results" tab and select schematic. Now trace to the inputs of the net and attach the snapshot of same here.

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
0 Kudos
Highlighted
Visitor
Visitor
8,371 Views
Registered: ‎10-14-2014

I believe you mean this then. Inside the module dma_fpga the signal is driven as shown in the next snapshot.

Untitled2.png
Untitled3.png
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
8,364 Views
Registered: ‎09-20-2012

Hi ,

 

Is PL_CLK defined as output port or input port in the design?

 

If it is defined as output port, it is not possible to drive this to PRE input pin of flops as shown in your second snapshot.

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
0 Kudos
Highlighted
Visitor
Visitor
8,360 Views
Registered: ‎10-14-2014

PL_CLK[1] as all the PL_CLK vector are defined as shown:

PL_CLK : inout std_logic_vector(3 downto 0);

 

Also if I synthesize and implement my design with ISE and without the use of partial reconfiguration and a Microblaze processor, everything runs smoothly. 

0 Kudos