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Participant jai_pandey
Participant
9,066 Views
Registered: ‎12-17-2009

MIG V 3.5 does not support correct LOC for MPMC 6.02a for ML507 with DDR2

Dear Friends! I am using EDK 12.4 to use MPMC for the 32 bit DDR2 (Micron, MT4HT3264HY-667) on ML-507 board

with Virtex-5 device(xc5vfx70t-1136). I have used this controller with three ports. One for the MCI to

PPC440, second for the VFBC Write and third one is for the VFBC read. I have used integrated MIG tool for  the ucf generation with PPC440 Option selected. The generated ucf file does not provides correct LOC. I have corrected the generated UCF file as per the ml50x_schematics file by xilinx . The modified ucf file is as follows:

############################################################################
##  MODIFIED FILE
##  Xilinx, Inc. 2006            www.xilinx.com
##  Tue Feb 22 12:00:08 2011
##  Generated by MIG Version 3.5
##  
############################################################################
##  File name :       DDR2_SDRAM.ucf
##
##  Details :     Constraints file
##                    FPGA family:       virtex5
##                    FPGA:              xc5vfx70t-ff1136
##                    Speedgrade:        -1
##                    Design Entry:      VERILOG
##                    Design:            without Test bench
##                    DCM Used:          Enable
##                    No.Of Controllers: 1
##
############################################################################

############################################################################
# Clock constraints                                                        #
############################################################################

NET "u_ddr2_infrastructure/sys_clk_ibufg" TNM_NET =  "SYS_CLK";
TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 5 ns HIGH 50 %;

NET "u_ddr2_infrastructure/clk200_ibufg" TNM_NET = "SYS_CLK_200";
TIMESPEC "TS_SYS_CLK_200" = PERIOD "SYS_CLK_200" 5 ns HIGH 50 %;

############################################################################

########################################################################
# Controller 0
# Memory Device: DDR2_SDRAM->Components->MT4HTF3264H-667 #
# Data Width:     32 #
# Data Mask:     1 #
########################################################################
################################################################################
# FX70T-FF1136 UCF for DDR2_SDRAM 32-bit Registered DIMM or component interface
################################################################################

################################################################################
# I/O STANDARDS
################################################################################

NET  "ddr2_dq[*]"                                    IOSTANDARD = SSTL18_II_DCI;
NET  "ddr2_a[*]"                                     IOSTANDARD = SSTL18_II;
NET  "ddr2_ba[*]"                                    IOSTANDARD = SSTL18_II;
NET  "ddr2_ras_n"                                    IOSTANDARD = SSTL18_II;
NET  "ddr2_cas_n"                                    IOSTANDARD = SSTL18_II;
NET  "ddr2_we_n"                                     IOSTANDARD = SSTL18_II;
#NET  "ddr2_reset_n"                                  IOSTANDARD = LVCMOS18;
NET  "ddr2_cs_n[*]"                                  IOSTANDARD = SSTL18_II;
NET  "ddr2_odt[*]"                                   IOSTANDARD = SSTL18_II;
NET  "ddr2_cke[*]"                                   IOSTANDARD = SSTL18_II;
NET  "ddr2_dm[*]"                                    IOSTANDARD = SSTL18_II_DCI;
NET  "sys_clk_p"                                     IOSTANDARD = LVPECL_25;
NET  "sys_clk_n"                                     IOSTANDARD = LVPECL_25;
NET  "clk200_p"                                      IOSTANDARD = LVPECL_25;
NET  "clk200_n"                                      IOSTANDARD = LVPECL_25;
#NET  "sys_rst_n"                                     IOSTANDARD = LVCMOS18;   # system reset ## Commented by Jai
#NET  "phy_init_done"                                 IOSTANDARD = LVCMOS18;                         ## Commented by Jai
NET  "ddr2_dqs[*]"                                   IOSTANDARD = DIFF_SSTL18_II_DCI;
NET  "ddr2_dqs_n[*]"                                 IOSTANDARD = DIFF_SSTL18_II_DCI;
NET  "ddr2_ck[*]"                                    IOSTANDARD = DIFF_SSTL18_II;
NET  "ddr2_ck_n[*]"                                  IOSTANDARD = DIFF_SSTL18_II;

################################################################################
# Location Constraints
################################################################################

#
#NET  <Memory Controller Signal>     LOC =   <Pin> ;   # <Board Signal name>  <FPGA Bank number>
# ----------------------------------------------------------------------------------------------


#NET      "sys_rst_n"     LOC =   "AE31" ;        # FPGA2_RESET_N  Bank 17  ## Commented by Jai
#NET      "phy_init_done" LOC =   "AD30" ;        #                Bank 17     ## Commented by Jai


#############################################################################
### Below Addded By Jai
##  As per the Schematic of ML507 (xilinx file ml50x_schematics) the MIG genarted LOC has neen changed


NET      "sys_clk_p"     LOC =   "H14" ;    # Bank 3    
NET      "sys_clk_n"     LOC =   "H15" ;    # Bank 3   
NET      "clk200_p"      LOC =   "J20" ;    # Bank 3     
NET      "clk200_n"      LOC =   "J21" ;    # Bank 3     

Net DDR2_Ck<0> LOC=AK29  |  IOSTANDARD = DIFF_SSTL18_II;
#Net DDR2_Ck<1> LOC=E28  |  IOSTANDARD = DIFF_SSTL18_II;
Net DDR2_Ck_n<0> LOC=AJ29  |  IOSTANDARD = DIFF_SSTL18_II;
#Net DDR2_Ck_n<1> LOC=F28  |  IOSTANDARD = DIFF_SSTL18_II;
Net DDR2_CKE LOC=T28  |  IOSTANDARD = SSTL18_II;        # Bank 15
Net DDR2_CS_n LOC=L29  |  IOSTANDARD = SSTL18_II;        # Bank 15
Net DDR2_ODT<0> LOC=F31  |  IOSTANDARD = SSTL18_II;    # Bank 15
Net DDR2_ODT<1> LOC=F30  |  IOSTANDARD = SSTL18_II;    # Bank 15
Net DDR2_RAS_n LOC=H30  |  IOSTANDARD = SSTL18_II;     # Bank 15
Net DDR2_CAS_n LOC=E31  |  IOSTANDARD = SSTL18_II;        # Bank 15
Net DDR2_WE_n LOC=K29  |  IOSTANDARD = SSTL18_II;        # Bank 15
Net DDR2_BA<0> LOC=G31  |  IOSTANDARD = SSTL18_II;        # Bank 15
Net DDR2_BA<1> LOC=J30  |  IOSTANDARD = SSTL18_II;        # Bank 15
Net DDR2_A<0> LOC=L30  |  IOSTANDARD = SSTL18_II;        # Bank 15
Net DDR2_A<1> LOC=M30  |  IOSTANDARD = SSTL18_II;        # Bank 15
Net DDR2_A<2> LOC=N29  |  IOSTANDARD = SSTL18_II;        # Bank 15
Net DDR2_A<3> LOC=P29  |  IOSTANDARD = SSTL18_II;        # Bank 15
Net DDR2_A<4> LOC=K31  |  IOSTANDARD = SSTL18_II;        # Bank 15
Net DDR2_A<5> LOC=L31  |  IOSTANDARD = SSTL18_II;        # Bank 15
Net DDR2_A<6> LOC=P31  |  IOSTANDARD = SSTL18_II;        # Bank 15
Net DDR2_A<7> LOC=P30  |  IOSTANDARD = SSTL18_II;        # Bank 15
Net DDR2_A<8> LOC=M31  |  IOSTANDARD = SSTL18_II;        # Bank 15
Net DDR2_A<9> LOC=R28  |  IOSTANDARD = SSTL18_II;        # Bank 15
Net DDR2_A<10> LOC=J31  |  IOSTANDARD = SSTL18_II;        # Bank 15
Net DDR2_A<11> LOC=R29  |  IOSTANDARD = SSTL18_II;        # Bank 15
Net DDR2_A<12> LOC=T31  |  IOSTANDARD = SSTL18_II;        # Bank 15

Net DDR2_DQ<0> LOC=AF30  |  IOSTANDARD = SSTL18_II;    # Bank 17
Net DDR2_DQ<1> LOC=AK31  |  IOSTANDARD = SSTL18_II;    # Bank 17
Net DDR2_DQ<2> LOC=AF31  |  IOSTANDARD = SSTL18_II;    # Bank 17
Net DDR2_DQ<3> LOC=AD30  |  IOSTANDARD = SSTL18_II;    # Bank 17
Net DDR2_DQ<4> LOC=AJ30  |  IOSTANDARD = SSTL18_II;    # Bank 17
Net DDR2_DQ<5> LOC=AF29  |  IOSTANDARD = SSTL18_II;    # Bank 17
Net DDR2_DQ<6> LOC=AD29  |  IOSTANDARD = SSTL18_II;    # Bank 17
Net DDR2_DQ<7> LOC=AE29  |  IOSTANDARD = SSTL18_II;    # Bank 17

Net DDR2_DQ<8> LOC=AH27  |  IOSTANDARD = SSTL18_II;    # Bank 21
Net DDR2_DQ<9> LOC=AF28  |  IOSTANDARD = SSTL18_II;    # Bank 21
Net DDR2_DQ<10> LOC=AH28  |  IOSTANDARD = SSTL18_II;    # Bank 21
Net DDR2_DQ<11> LOC=AA28  |  IOSTANDARD = SSTL18_II;    # Bank 21
Net DDR2_DQ<12> LOC=AG25  |  IOSTANDARD = SSTL18_II;    # Bank 21
Net DDR2_DQ<13> LOC=AJ26  |  IOSTANDARD = SSTL18_II;    # Bank 21
Net DDR2_DQ<14> LOC=AG28  |  IOSTANDARD = SSTL18_II;    # Bank 21
Net DDR2_DQ<15> LOC=AB28  |  IOSTANDARD = SSTL18_II;    # Bank 21
Net DDR2_DQ<16> LOC=AC28  |  IOSTANDARD = SSTL18_II;    # Bank 21
Net DDR2_DQ<17> LOC=AB25  |  IOSTANDARD = SSTL18_II;    # Bank 21
Net DDR2_DQ<18> LOC=AC27  |  IOSTANDARD = SSTL18_II;    # Bank 21
Net DDR2_DQ<19> LOC=AA26  |  IOSTANDARD = SSTL18_II;    # Bank 21
Net DDR2_DQ<20> LOC=AB26  |  IOSTANDARD = SSTL18_II;    # Bank 21
Net DDR2_DQ<21> LOC=AA24  |  IOSTANDARD = SSTL18_II;    # Bank 21
Net DDR2_DQ<22> LOC=AB27  |  IOSTANDARD = SSTL18_II;    # Bank 21
Net DDR2_DQ<23> LOC=AA25  |  IOSTANDARD = SSTL18_II;    # Bank 21

Net DDR2_DQ<24> LOC=AC29  |  IOSTANDARD = SSTL18_II;    # Bank 17
Net DDR2_DQ<25> LOC=AB30  |  IOSTANDARD = SSTL18_II;    # Bank 17
Net DDR2_DQ<26> LOC=W31  |  IOSTANDARD = SSTL18_II;    # Bank 17
Net DDR2_DQ<27> LOC=V30  |  IOSTANDARD = SSTL18_II;    # Bank 17
Net DDR2_DQ<28> LOC=AC30  |  IOSTANDARD = SSTL18_II;    # Bank 17
Net DDR2_DQ<29> LOC=W29  |  IOSTANDARD = SSTL18_II;    # Bank 17
Net DDR2_DQ<30> LOC=V27  |  IOSTANDARD = SSTL18_II;    # Bank 17
Net DDR2_DQ<31> LOC=W27  |  IOSTANDARD = SSTL18_II;    # Bank 17

Net DDR2_DM<0> LOC=AJ31  |  IOSTANDARD = SSTL18_II;    # Bank 17

Net DDR2_DM<1> LOC=AE28  |  IOSTANDARD = SSTL18_II;    # Bank 21
Net DDR2_DM<2> LOC=Y24  |  IOSTANDARD = SSTL18_II;        # Bank 21

Net DDR2_DM<3> LOC=Y31  |  IOSTANDARD = SSTL18_II;                # Bank 17
Net DDR2_DQS<0> LOC=AA29  |  IOSTANDARD = DIFF_SSTL18_II;     # Bank 17


Net DDR2_DQS<1> LOC=AK28  |  IOSTANDARD = DIFF_SSTL18_II;     # Bank 21
Net DDR2_DQS<2> LOC=AK26  |  IOSTANDARD = DIFF_SSTL18_II;    # Bank 21

Net DDR2_DQS<3> LOC=AB31  |  IOSTANDARD = DIFF_SSTL18_II;    # Bank 17

Net DDR2_DQS_n<0> LOC=AA30  |  IOSTANDARD = DIFF_SSTL18_II;    # Bank 17
Net DDR2_DQS_n<1> LOC=AK27  |  IOSTANDARD = DIFF_SSTL18_II;    # Bank 21
Net DDR2_DQS_n<2> LOC=AJ27  |  IOSTANDARD = DIFF_SSTL18_II;    # Bank 21
Net DDR2_DQS_n<3> LOC=AA31  |  IOSTANDARD = DIFF_SSTL18_II;    # Bank 17

Net sys_clk TNM_NET = sys_clk;
TIMESPEC TS_sys_clk = PERIOD sys_clk 100000 kHz;
Net sys_clk LOC = AH15  |  IOSTANDARD=LVCMOS33;        # Bank 4
Net sys_rst_s TIG;
Net sys_rst_s LOC = E9  |  IOSTANDARD=LVCMOS33  |  PULLUP; # Bank 20


########## Above Addded By Jai  ########################



## Generated by MIG tool

############################################################################
# AREA_GROUP Constraint
############################################################################

#INST "u_ddr2_top/*" AREA_GROUP="AREA_DDR2"; AREA_GROUP "AREA_DDR2" RANGE=SLICE_X0Y0:SLICE_X15Y100;

############################################################################
#  BRAM Location Constraints
############################################################################

#INST "*/.gen_rdf[0].u_rdf" LOC  = RAMB36_X0Y19;
#INST "*/.gen_rdf[0].u_rdf1" LOC = RAMB36_X0Y18;
#INST "*/.gen_wdf[0].u_usr_wr_fifo/.u_wdf" LOC = RAMB36_X0Y17;
################################################################################
#IDELAYCTRL Location Constraints
################################################################################

# INST "*/IDELAYCTRL_INST[0].u_idelayctrl" LOC=IDELAYCTRL_X0Y3;
# INST "*/IDELAYCTRL_INST[1].u_idelayctrl" LOC=IDELAYCTRL_X0Y4;

###############################################################################
# Define multicycle paths - these paths may take longer because additional
# time allowed for logic to settle in calibration/initialization FSM
###############################################################################

# MIG 2.1: Eliminate Timegroup definitions for CLK0, and CLK90. Instead trace
#          multicycle paths from originating flip-flop to ANY destination
#          flip-flop (or in some cases, it can also be a BRAM)
# MUX Select for either rising/falling CLK0 for 2nd stage read capture
INST "*/u_phy_calib/gen_rd_data_sel*.u_ff_rd_data_sel" TNM = "TNM_RD_DATA_SEL";
TIMESPEC "TS_MC_RD_DATA_SEL" = FROM "TNM_RD_DATA_SEL" TO FFS
"TS_SYS_CLK" * 4;
# MUX select for read data - optional delay on data to account for byte skews
INST "*/u_usr_rd/gen_rden_sel_mux*.u_ff_rden_sel_mux" TNM = "TNM_RDEN_SEL_MUX";
TIMESPEC "TS_MC_RDEN_SEL_MUX" = FROM "TNM_RDEN_SEL_MUX" TO FFS
"TS_SYS_CLK" * 4;
# Calibration/Initialization complete status flag (for PHY logic only) - can
# be used to drive both flip-flops and BRAMs
INST "*/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_DATA_SEL";
TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_0" = FROM "TNM_PHY_INIT_DATA_SEL" TO FFS
"TS_SYS_CLK" * 4;
# The RAM path is only used in cases where Write Latency (Additive Latency +
# (CAS Latency - 1) + (1 in case of RDIMM)) is 2 or below. So these constraints are
# valid for CAS Latency = 3, Additive Latency = 0 and selected part is not RDIMM.
# If Write Latency is higher than 3, then a warning will appear in PAR,
# and the constraint can be ignored as this path does not exist. RAM constraint
# can be safely removed if the warning is not to be displayed.
TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_90" = FROM "TNM_PHY_INIT_DATA_SEL" TO RAMS
"TS_SYS_CLK" * 4;
# Select (address) bits for SRL32 shift registers used in stage3/stage4
# calibration
INST "*/u_phy_calib/gen_gate_dly*.u_ff_gate_dly" TNM = "TNM_GATE_DLY";
TIMESPEC "TS_MC_GATE_DLY" = FROM "TNM_GATE_DLY" TO FFS "TS_SYS_CLK" * 4;

INST "*/u_phy_calib/gen_rden_dly*.u_ff_rden_dly" TNM = "TNM_RDEN_DLY";
TIMESPEC "TS_MC_RDEN_DLY" = FROM "TNM_RDEN_DLY" TO FFS "TS_SYS_CLK" * 4;

INST "*/u_phy_calib/gen_cal_rden_dly*.u_ff_cal_rden_dly"
  TNM = "TNM_CAL_RDEN_DLY";
TIMESPEC "TS_MC_CAL_RDEN_DLY" = FROM "TNM_CAL_RDEN_DLY" TO FFS
"TS_SYS_CLK" * 4;
###############################################################################
#The following constraint is added to prevent (false) hold time violations on
#the data path from stage1 to stage2 capture flops.  Stage1 flops are clocked by
#the delayed DQS and stage2 flops are clocked by the clk0 clock. Placing a TIG
#on the DQ IDDR capture flop instance to achieve this is acceptable because timing
#is guaranteed through the use of separate Predictable IP constraints. These
#violations are reported when anunconstrained path report is run.      
###############################################################################
INST "*/gen_dq[*].u_iob_dq/gen*.u_iddr_dq" TIG ;
###############################################################################
# DQS Read Post amble Glitch Squelch circuit related constraints
###############################################################################

###############################################################################
# LOC placement of DQS-squelch related IDDR and IDELAY elements
# Each circuit can be located at any of the following locations:
#  1. Unused "N"-side of DQS differential pair I/O
#  2. DM data mask (output only, input side is free for use)
#  3. Any output-only site
###############################################################################

###############################################################################
#The following constraint is added to avoid the HOLD violations in the trace report
#when run for unconstrained paths.These two FF groups will be clocked by two different
# clocks and hence there should be no timing analysis performed on this path.
###############################################################################
INST "*/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[*].u_en_dqs_ff" TNM = EN_DQS_FF;
TIMESPEC TS_FROM_EN_DQS_FF_TO_DQ_CE_FF = FROM EN_DQS_FF TO TNM_DQ_CE_IDDR 3.85 ns DATAPATHONLY;

INST "*/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce"  LOC = "ILOGIC_X0Y140";
INST "*/gen_dqs[0].u_iob_dqs/u_iodelay_dq_ce"  LOC = "IODELAY_X0Y140";
INST "*/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce"  LOC = "ILOGIC_X0Y176";
INST "*/gen_dqs[1].u_iob_dqs/u_iodelay_dq_ce"  LOC = "IODELAY_X0Y176";
INST "*/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce"  LOC = "ILOGIC_X0Y180";
INST "*/gen_dqs[2].u_iob_dqs/u_iodelay_dq_ce"  LOC = "IODELAY_X0Y180";
INST "*/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce"  LOC = "ILOGIC_X0Y178";
INST "*/gen_dqs[3].u_iob_dqs/u_iodelay_dq_ce"  LOC = "IODELAY_X0Y178";

###############################################################################
# LOC and timing constraints for flop driving DQS CE enable signal
# from fabric logic. Even though the absolute delay on this path is
# calibrated out (when synchronizing this output to DQS), the delay
# should still be kept as low as possible to reduce post-calibration
# voltage/temp variations - these are roughly proportional to the
# absolute delay of the path.                                    
#    The following code has been commented for V5 as the predictable IP will take
#    care of placement of these flops by meeting the MAXDELAY requirement.  
#    These constraints will be removed in the next release.  
###############################################################################

INST "*/u_phy_calib/gen_gate[0].u_en_dqs_ff"  LOC = SLICE_X0Y70;
INST "*/u_phy_calib/gen_gate[1].u_en_dqs_ff"  LOC = SLICE_X0Y88;
INST "*/u_phy_calib/gen_gate[2].u_en_dqs_ff"  LOC = SLICE_X0Y90;
INST "*/u_phy_calib/gen_gate[3].u_en_dqs_ff"  LOC = SLICE_X0Y89;

# Control for DQS gate - from fabric flop. Prevent "runaway" delay -
# two parts to this path: (1) from fabric flop to IDELAY, (2) from
# IDELAY to asynchronous reset of IDDR that drives the DQ CE's
# This can be relaxed by the user for lower frequencies:
# 300MHz = 850ps, 267MHz = 900ps. At 200MHz = 950ps.
# In general PAR should be able to route this
# within 900ps over all speed grades.
NET "*/u_phy_io/en_dqs[*]" MAXDELAY = 600 ps;
NET "*/u_phy_io/gen_dqs*.u_iob_dqs/en_dqs_sync" MAXDELAY = 850 ps;

###############################################################################
# "Half-cycle" path constraint from IOB flip-flop to CE pin for all DQ IDDR's
# for DQS Read Post amble Glitch Squelch circuit
###############################################################################

# Max delay from output of IOB flip-flop to CE input of DQ IDDRs =
#  tRPST + some slack where slack account for rise-time of DQS on board.
#  For now assume slack = 0.400ns (based on initial SPICE simulations,
#  assumes use of ODT), so time = 0.4*Tcyc + 0.40ns = 1.6ns @333MHz
INST "*/gen_dqs[*].u_iob_dqs/u_iddr_dq_ce" TNM = "TNM_DQ_CE_IDDR";
INST "*/gen_dq[*].u_iob_dq/gen_stg2_*.u_iddr_dq" TNM = "TNM_DQS_FLOPS";
TIMESPEC "TS_DQ_CE" = FROM "TNM_DQ_CE_IDDR" TO "TNM_DQS_FLOPS" 2.4 ns;

When I have again used the integrated MIG tool to verify the Modified ucf it shows error. In error message it says that the modified  UCF should follow the same banks, which is not the correct banks. The error message is:

 

Verification Report
Generated by MIG Version 3.5 on Tue Feb 22 12:50:19 2011
Reading design libraries of xc5vfx70t-ff1136... successful !
/*******************************************************/
/* Controller 0
/*******************************************************/
MIG will update IDDR and IDELAY location in UCF based on distance between these signals( DQ to DM and DQ to DQS).
DM signal is most nearest to DQ signal for data set0.
DQS signal is most nearest to DQ signal for data set1.
DM signal is most nearest to DQ signal for data set2.
DQS signal is most nearest to DQ signal for data set3.
ERROR: DDR2_DQ[0](Data) should not be allocated to bank 17. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[1](Data) should not be allocated to bank 17. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[2](Data) should not be allocated to bank 17. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[3](Data) should not be allocated to bank 17. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[4](Data) should not be allocated to bank 17. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[5](Data) should not be allocated to bank 17. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[6](Data) should not be allocated to bank 17. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[7](Data) should not be allocated to bank 17. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[8](Data) should not be allocated to bank 21. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[9](Data) should not be allocated to bank 21. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[10](Data) should not be allocated to bank 21. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[11](Data) should not be allocated to bank 21. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[12](Data) should not be allocated to bank 21. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[13](Data) should not be allocated to bank 21. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[14](Data) should not be allocated to bank 21. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[15](Data) should not be allocated to bank 21. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[16](Data) should not be allocated to bank 21. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[17](Data) should not be allocated to bank 21. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[18](Data) should not be allocated to bank 21. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[19](Data) should not be allocated to bank 21. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[20](Data) should not be allocated to bank 21. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[21](Data) should not be allocated to bank 21. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[22](Data) should not be allocated to bank 21. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[23](Data) should not be allocated to bank 21. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[24](Data) should not be allocated to bank 17. The rule is, it can only be moved within the bank(s) "11,13"
1
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[25](Data) should not be allocated to bank 17. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[26](Data) should not be allocated to bank 17. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[27](Data) should not be allocated to bank 17. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[28](Data) should not be allocated to bank 17. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[29](Data) should not be allocated to bank 17. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[30](Data) should not be allocated to bank 17. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQ[31](Data) should not be allocated to bank 17. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_A[12](Address) should not be allocated to bank 15. The rule is, it can only be moved within the bank(s) "11,13,17"
specified in the input mig.prj file for "Address" group.
ERROR: DDR2_A[11](Address) should not be allocated to bank 15. The rule is, it can only be moved within the bank(s) "11,13,17"
specified in the input mig.prj file for "Address" group.
ERROR: DDR2_A[10](Address) should not be allocated to bank 15. The rule is, it can only be moved within the bank(s) "11,13,17"
specified in the input mig.prj file for "Address" group.
ERROR: DDR2_A[9](Address) should not be allocated to bank 15. The rule is, it can only be moved within the bank(s) "11,13,17"
specified in the input mig.prj file for "Address" group.
ERROR: DDR2_A[8](Address) should not be allocated to bank 15. The rule is, it can only be moved within the bank(s) "11,13,17"
specified in the input mig.prj file for "Address" group.
ERROR: DDR2_A[7](Address) should not be allocated to bank 15. The rule is, it can only be moved within the bank(s) "11,13,17"
specified in the input mig.prj file for "Address" group.
ERROR: DDR2_A[6](Address) should not be allocated to bank 15. The rule is, it can only be moved within the bank(s) "11,13,17"
specified in the input mig.prj file for "Address" group.
ERROR: DDR2_A[5](Address) should not be allocated to bank 15. The rule is, it can only be moved within the bank(s) "11,13,17"
specified in the input mig.prj file for "Address" group.
ERROR: DDR2_A[4](Address) should not be allocated to bank 15. The rule is, it can only be moved within the bank(s) "11,13,17"
specified in the input mig.prj file for "Address" group.
ERROR: DDR2_A[3](Address) should not be allocated to bank 15. The rule is, it can only be moved within the bank(s) "11,13,17"
specified in the input mig.prj file for "Address" group.
ERROR: DDR2_A[2](Address) should not be allocated to bank 15. The rule is, it can only be moved within the bank(s) "11,13,17"
specified in the input mig.prj file for "Address" group.
ERROR: DDR2_A[1](Address) should not be allocated to bank 15. The rule is, it can only be moved within the bank(s) "11,13,17"
specified in the input mig.prj file for "Address" group.
ERROR: DDR2_A[0](Address) should not be allocated to bank 15. The rule is, it can only be moved within the bank(s) "11,13,17"
specified in the input mig.prj file for "Address" group.
ERROR: DDR2_BA[1](BankAddress) should not be allocated to bank 15. The rule is, it can only be moved within the bank(s)
"11,13,17" specified in the input mig.prj file for "Address" group.
ERROR: DDR2_BA[0](BankAddress) should not be allocated to bank 15. The rule is, it can only be moved within the bank(s)
"11,13,17" specified in the input mig.prj file for "Address" group.
ERROR: DDR2_RAS_n(Control) should not be allocated to bank 15. The rule is, it can only be moved within the bank(s) "11,13,17"
specified in the input mig.prj file for "Address" group.
ERROR: DDR2_CAS_n(Control) should not be allocated to bank 15. The rule is, it can only be moved within the bank(s) "11,13,17"
specified in the input mig.prj file for "Address" group.
ERROR: DDR2_WE_n(Control) should not be allocated to bank 15. The rule is, it can only be moved within the bank(s) "11,13,17"
specified in the input mig.prj file for "Address" group.
WARNING: Signal ddr2_cs_n[0] expected, but not present in the UCF.
WARNING: Signal ddr2_cs_n[1] expected, but not present in the UCF.
WARNING: Signal ddr2_cs_n[2] expected, but not present in the UCF.
WARNING: Signal ddr2_cs_n[3] expected, but not present in the UCF.
ERROR: DDR2_ODT[0](Control) should not be allocated to bank 15. The rule is, it can only be moved within the bank(s) "11,13,17"
specified in the input mig.prj file for "Address" group.
ERROR: DDR2_ODT[1](Control) should not be allocated to bank 15. The rule is, it can only be moved within the bank(s) "11,13,17"
specified in the input mig.prj file for "Address" group.
WARNING: Signal ddr2_odt[2] expected, but not present in the UCF.
WARNING: Signal ddr2_odt[3] expected, but not present in the UCF.
WARNING: Signal ddr2_cke[0] expected, but not present in the UCF.
ERROR: DDR2_DM[0](Mask) should not be allocated to bank 17. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DM[1](Mask) should not be allocated to bank 21. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DM[2](Mask) should not be allocated to bank 21. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DM[3](Mask) should not be allocated to bank 17. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: clk200_p(System_Clock) should not be allocated to bank 3. The rule is, it can only be moved within the bank(s) "4"
specified in the input mig.prj file for "System_Clock" group.
ERROR: clk200_n(System_Clock) should not be allocated to bank 3. The rule is, it can only be moved within the bank(s) "4"
specified in the input mig.prj file for "System_Clock" group.
WARNING: Signal sys_rst_n expected, but not present in the UCF.
WARNING: Signal phy_init_done expected, but not present in the UCF.
ERROR: DDR2_DQS[0](Strobe) should not be allocated to bank 17. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQS_n[0](Strobe) should not be allocated to bank 17. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQS[1](Strobe) should not be allocated to bank 21. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQS_n[1](Strobe) should not be allocated to bank 21. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQS[2](Strobe) should not be allocated to bank 21. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQS_n[2](Strobe) should not be allocated to bank 21. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQS[3](Strobe) should not be allocated to bank 17. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_DQS_n[3](Strobe) should not be allocated to bank 17. The rule is, it can only be moved within the bank(s) "11,13"
specified in the input mig.prj file for "Data" group.
ERROR: DDR2_Ck[0](Clock) should not be allocated to bank 21. The rule is, it can only be moved within the bank(s) "11,13,17"
specified in the input mig.prj file for "Address" group.
ERROR: DDR2_Ck_n[0](Clock) should not be allocated to bank 21. The rule is, it can only be moved within the bank(s) "11,13,17"
specified in the input mig.prj file for "Address" group.
WARNING: Signal ddr2_ck[1] expected, but not present in the UCF.
WARNING: Signal ddr2_ck_n[1] expected, but not present in the UCF.
WARNING: Signal ddr2_ck[2] expected, but not present in the UCF.
WARNING: Signal ddr2_ck_n[2] expected, but not present in the UCF.
WARNING: Signal ddr2_ck[3] expected, but not present in the UCF.
WARNING: Signal ddr2_ck_n[3] expected, but not present in the UCF.
Verification completed.
Number of pin allocation errors = 68.

 

The .prj file is as:

 

<?xml version="1.0" encoding="UTF-8"?>
<Project NoOfControllers="1" >
    <PLL>1</PLL>
    <ModuleName>DDR2_SDRAM</ModuleName>
    <TwoByteSel>0</TwoByteSel>
    <dci_inouts_inputs>1</dci_inouts_inputs>
    <dci_outputs>0</dci_outputs>
    <Class>Class II</Class>
    <Debug_En>Disable</Debug_En>
    <TargetFPGA>xc5vfx70t-ff1136/-1</TargetFPGA>
    <Version>3.5</Version>
    <PPC440>1</PPC440>
    <PPCBlockType>Top</PPCBlockType>
    <PinSelectionFlag>FALSE</PinSelectionFlag>
    <IODelayHighPerformanceMode>HIGH</IODelayHighPerformanceMode>
    <Controller number="0" >
        <MemoryDevice>DDR2_SDRAM/Components/MT4HTF3264H-667</MemoryDevice>
        <TimePeriod>5000</TimePeriod>
        <DataWidth>32</DataWidth>
        <DeepMemory>1</DeepMemory>
        <CustomPart>FALSE</CustomPart>
        <NewPartName></NewPartName>
        <RowAddress>13</RowAddress>
        <ColAddress>10</ColAddress>
        <BankAddress>2</BankAddress>
        <TimingParameters>
            <Parameters tdsa="300" tjit="125" tdsb="100" twtr="7.5" tis="400" twr="15" trtp="7.5" tdha="300" trfc="197.5" trp="15" tdhb="175" tmrd="2" tih="400" tras="40" trcd="15" tac="450" />
        </TimingParameters>
        <ECC>ECC Disabled</ECC>
        <BankSelection>
            <Bank Control="0" SysClk="0" Data="1" name="11" Address="1" wasso="38" />
            <Bank Control="0" SysClk="0" Data="1" name="13" Address="1" wasso="38" />
            <Bank Control="1" SysClk="0" Data="0" name="17" Address="1" wasso="38" />
            <Bank Control="0" SysClk="1" Data="0" name="4" Address="0" wasso="19" />
        </BankSelection>
        <mrBurstLength name="Burst Length" >4(010)</mrBurstLength>
        <mrBurstType name="Burst Type" >sequential(0)</mrBurstType>
        <mrCasLatency name="CAS Latency" >3(011)</mrCasLatency>
        <mrMode name="Mode" >normal(0)</mrMode>
        <mrDllReset name="DLL Reset" >no(0)</mrDllReset>
        <mrPdMode name="PD Mode" >fast exit(0)</mrPdMode>
        <mrWriteRecovery name="Write Recovery" >3(010)</mrWriteRecovery>
        <emrDllEnable name="DLL Enable" >Enable-Normal(0)</emrDllEnable>
        <emrOutputDriveStrength name="Output Drive Strength" >Fullstrength(0)</emrOutputDriveStrength>
        <emrRTT name="RTT (nominal) - ODT" >75ohms(01)</emrRTT>
        <emrPosted name="Additive Latency (AL)" >0(000)</emrPosted>
        <emrOCD name="OCD Operation" >OCD Exit(000)</emrOCD>
        <emrDQS name="DQS# Enable" >Enable(0)</emrDQS>
        <emrRDQS name="RDQS Enable" >Disable(0)</emrRDQS>
        <emrOutputs name="Outputs" >Enable(0)</emrOutputs>
    </Controller>
</Project>

To bypass the message I have cleaned the hardware, netlist and bits and again run to generate netlist I am getting the following error.


ERROR:EDK:3900 - issued from TCL procedure
   "::hw_mpmc_v6_02_a::syslevel_drc_mig_flow" line 88
   C_USE_MIG_FLOW (IPNAME:mpmc, INSTANCE:DDR2_SDRAM) - There have been changes
   to this design that have changed the number of external memory pins for MPMC
   instance DDR2_SDRAM.  Please re-run the MIG gui from the IP Configurator to
   generate the correct constraints.


Please let me know how can I obtain the correct ucf with all the necessary timing parameters setting. Please provide me the correct ucf. I also wish to know the IDELAYCTRL related settings for the  MPMC.

Encl. All required files

 

Thanks in advance

Regards

Jai

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8 Replies
Explorer
Explorer
9,039 Views
Registered: ‎08-02-2007

Re: MIG V 3.5 does not support correct LOC for MPMC 6.02a for ML507 with DDR2

The reason for the MIG verify errors is that the MIG.prj file contains all of the original MIG selections for the project when it was created.  This specifies valid banking rules for each pin type and can be seen in the mig.prj snippet as follows:

 

            <Bank Control="0" SysClk="0" Data="1" name="11" Address="1" wasso="38" />
            <Bank Control="0" SysClk="0" Data="1" name="13" Address="1" wasso="38" />
            <Bank Control="1" SysClk="0" Data="0" name="17" Address="1" wasso="38" />
            <Bank Control="0" SysClk="1" Data="0" name="4" Address="0" wasso="19" />

 

As you can see, the first line (name="11", or bank 11) will support Data and Address pins (="1") but will not support bank control pins or sysclk pins and will error if you try to attach any of these pin types to these banks.  In order to get around these errors, you can either:

 

a.) create a new MIG design that will allow the banking rules per your new pinout and use that to import the new pin requirements

b.) manually change the mig.prj file.  This may be more simple then suggestion 'a' but I cannot guarantee the results since hacking away at the .prj file could lead to other issues if not done properly.

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Participant jai_pandey
Participant
9,033 Views
Registered: ‎12-17-2009

Re: MIG V 3.5 does not support correct LOC for MPMC 6.02a for ML507 with DDR2

Thanks for your succinct reply. I per your suggestions I have tried both the techniques. In both ways when I use the MIG tool to VERIFY UCF and UPDATE DESIGN AND UCF, the MIG tool regenerates the ucf will the desired BANK but with incorrect LOC. If I do not use VERIFY UCF and UPDATE DESIGN AND UCF tool the EDK says that there has been changes in MIG portion of the design and it require to rerun the MIG.

Please resolve the issue and help me to get correct ucf by MIG.

For your kind information the BSB with MPMC generates correct ucf . But sine I need MPMC with 32 bit DDR2 and with three ports I am using MIG to generate ucf for the mpmc.

Thanks

Regards Jai

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Explorer
Explorer
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Registered: ‎08-02-2007

Re: MIG V 3.5 does not support correct LOC for MPMC 6.02a for ML507 with DDR2

What do you mean when you state that the update design flow generates "incorrect LOC"?  Please expand on this statement.  are you receiving some error message when using the new updated MIG constraint file?

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Participant jai_pandey
Participant
8,999 Views
Registered: ‎12-17-2009

Re: MIG V 3.5 does not support correct LOC for MPMC 6.02a for ML507 with DDR2

In EDK system assembly view I have used MPMC IP GUI to configure it. In MPMC/ Memory Interface/ MIG settings tab, I have selected use Integrated MIG GUI flow and launch MIG. In this flow I have selected MIG output options to create design. The targeted device xc5vfx70t -ff1136-1 has been selected. I have selected PPC440 based memory controller further with all the defaults options MIG tool has generated DDR2.ucf file in :
C:\My_Design_DDr2t\__xps\mig\gui\DDR2_SDRAM\user_design\par\DDR2_SDRAM.ucf.
For example MIG create design has generated
NET "ddr2_a[0]" LOC = "AC34" ; # DDR2_A0 Bank 13
NET "ddr2_a[1]" LOC = "AD34" ; # DDR2_A1 Bank 13
NET "ddr2_a[2]" LOC = "AC32" ; # DDR2_A2 Bank 13
NET "ddr2_a[3]" LOC = "AB32" ; # DDR2_A3 Bank 13
NET "ddr2_a[4]" LOC = "AC33" ; # DDR2_A4 Bank 13
.
.
. ................... T
The Bank selection portion of the .prj file in the folder C:\My_Design_DDr2t\__xps\mig\gui\DDR2_SDRAM\user_design\mig.prj is as follows: Knowing the schematic of ML507:
We know which pins and which FPGA banks are used for the DDR2. For example:
NET "dd2_a[0]" LOC="L30" # Bank 15
Net "dd2_a[1]" LOC=M30 # Bank 15
Net "dd2_a[2]" LOC=N29 # Bank 15
Net "dd2_a[3]" LOC=P29 # Bank 15
Net "dd2_a[4]" LOC=K31 # Bank 15
.
. .......................
Since we have selected PPC440 based memory controller design in MIG create design flow,in this flow thereis no control to select the desired banks. Therefore as per your suggestion I have modified the Bank selection portion of .prj file as:
BankSelection>
            <Bank Control="0" SysClk="0" Data="0" name="15" Address="1" wasso="38" />
            <Bank Control="0" SysClk="0" Data="1" name="17" Address="0" wasso="38" />
            <Bank Control="0" SysClk="0" Data="1" name="21" Address="1" wasso="38" />
            <Bank Control="0" SysClk="1" Data="0" name="3" Address="0" wasso="19" />
        </BankSelection>
After this I have again used the MIG tool to VERIFY UCF and UPDATE DESIGN AND UCF, the MIG tool regenerates the ucf file with incorrect FPGA pins for example:
NET "ddr2_a[0]" LOC = "AC34" ; #Bank 13
NET "ddr2_a[1]" LOC = "AD34" ; #Bank 13
NET "ddr2_a[2]" LOC = "AC32" ; #Bank 13
NET "ddr2_a[3]" LOC = "AB32" ; #Bank 13
NET "ddr2_a[4]" LOC = "AC33" ; #Bank 13
...
.........
Which is not as per the schematic file of ML50x. If I do not use verification step of mig it generates the following error:
EDK:3900 - issued from TCL procedure "::hw_mpmc_v6_02_a::syslevel_drc_mig_flow" line 88 C_USE_MIG_FLOW (IPNAME:mpmc, INSTANCE:DDR2_SDRAM) - There have been changes to this design that have changed the number of external memory pins for MPMC instance DDR2_SDRAM. Please re-run the MIG gui from the IP Configurator to generate the correct constraints.
Is MIG does not allow to correct the FPGA pins ? can we say that "MIG V 3.5 does not support correct LOC(FPGA Pins) for MPMC 6.02a for ML507 with DDR2". Please correct me if there is anyy mistake.
I will be very thankful to you for your valuable time.
Regards
Jai
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Participant jai_pandey
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8,787 Views
Registered: ‎12-17-2009

Re: MIG V 3.5 does not support correct LOC for MPMC 6.02a for ML507 with DDR2

Dear All, Any update? I am still waiting for the help. Thanks
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Explorer
Explorer
8,776 Views
Registered: ‎08-02-2007

Re: MIG V 3.5 does not support correct LOC for MPMC 6.02a for ML507 with DDR2

Did you already check this - http://www.xilinx.com/support/answers/38680.htm

 

Other then that I'm not sure why it is replacing your selected pinout banks

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Participant jai_pandey
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8,766 Views
Registered: ‎12-17-2009

Re: MIG V 3.5 does not support correct LOC for MPMC 6.02a for ML507 with DDR2

Yes I have gone through the above answer support. I am waiting for the help for the correct MIG output . If anybody have done please let me know what went wrong in my design? Thanks
Tags (3)
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Participant jai_pandey
Participant
8,675 Views
Registered: ‎12-17-2009

Re: MIG V 3.5 does not support correct LOC for MPMC 6.02a for ML507 with DDR2

Is there any update? I will be glad to see any suggestion. Thanks
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