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Participant circuitbent
Participant
4,609 Views
Registered: ‎09-23-2008

MIG v2.3 addressing

First a little background: I have a system with a DDR controller running at 85 MHz that clears calibration and all.  My memory has 9 col, 13 row, and 2 bank bits (24 total) and is 32 bits wide.  My burst length is set to 2.

 

I have the addressing set up as follows:

Addr(23 downto 0)   <= Address(25 downto 3) & "0";
Addr(31 downto 24) <= (others => '0');

The command will be joined with Addr to be sent to the cntrl0_app_af_addr signal.  I want to only access addresses on the 64 bit boundaries hence the additional '0' at the end.

 

This set up works for lower addressed values but as soon as I access addresses in the upper range I read back incorrect values.  MIG documentation leads me to believe that it is handling all the refresh and precharging and I need not to concern myself with that.  Would there be any other reason why only the higher addresses operate incorrectly?

 

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Xilinx Employee
Xilinx Employee
4,606 Views
Registered: ‎10-23-2007

Re: MIG v2.3 addressing

Which FPGA family is this?  When you say "upper range", exactly what do you mean?  When it crosses to the next row?  In other words, precisely which address range is good and which is not?
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Participant circuitbent
Participant
4,607 Views
Registered: ‎09-23-2008

Re: MIG v2.3 addressing

Thanks for the quick reply!  I'm using a Virtex-4.

 

I did some small memory tests to check that MIG was working correctly and everything worked for the lower addresses (like around 0x1000 and below) but when I did a complete write to memory and read it all back it would fail at random addresses (0x00079318, 0x0005E888, 0x0007E448, 0x0013FB88) After the first fail it would fail sporadically and then continuously when it hits really high addresses like 0x02000000ish. 

 

edit: In other words, there is no precise address where it starts to fail.

 

 

Message Edited by circuitbent on 09-02-2009 10:43 AM
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Xilinx Employee
Xilinx Employee
4,576 Views
Registered: ‎10-23-2007

Re: MIG v2.3 addressing

I believe V4 has a fairly generic addressing scheme and you shouldn't have to worry about any boundaries.  I could be wrong though.  But I wonder if you are barking up the wrong tree.  Intermittent behavior wouldn't likely be caused by an address boundary.  If you keep reading those low words, do they too eventually fail?  Is this time related and the part is heating up?  It is odd that it fails more later.  What kind of failures do you see?  Bit errors or whole word errors?  Have you tried using the MIG example design and let it run for a bit to see if it triggers on any errors?

 

Also, what frequency are you using and what device speed grade do you have?

Message Edited by jspaldings on 09-02-2009 05:36 PM
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Participant circuitbent
Participant
4,561 Views
Registered: ‎09-23-2008

Re: MIG v2.3 addressing

I'm running everything at 85 MHz.  I'm aware that the speed is rather slow but it is above JEDEC's minimum of 83.33 MHz minimum even if just slightly.  It is DDR333 memory.

 

If I keep reading the low words they do not fail and is not time related.  The failures I see appear to be bit errors because the value is semi-correct although a few bits will be off.  I haven't used the example design at all and I'm not sure what it is there for.

 

It is also my understanding that I can treat bit 10 of the address like a normal addressing bit rather than the unsupported auto-precharge bit that needs to be tied low, correct? Or do I need to tie it low? (view http://www.xilinx.com/support/answers/24432.htm )  My MIG v2.3 user guide says I can use linear addressing which I'm assuming is that I don't need to tie any bits low and just use the address space as normal..?

 

 

Edit:  Do I need to precharge on my own when I switch rows or does MIG handle that automatically?   Also, when an address space fails it does not necessarily fail again on a second pass.

Message Edited by circuitbent on 09-03-2009 08:23 AM
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Xilinx Employee
Xilinx Employee
4,550 Views
Registered: ‎10-23-2007

Re: MIG v2.3 addressing

The example design is there to provide a simulation example and to test the interface standalone to help isolate issues.  It is not an exhaustive memory tester, but if it works standalone you should have reasonable confidence that the interface is funcitoning properly.

 

I believe that the V4 design does indeed have linear addressing.  You do not need to precharge or activate as the core does that for you.

 

What you are describing sounds a bit like a calibration or signal integrity issue since it causes bit errors and is intermittent.  The counter to this is that various address ranges behave differently which says the DQ bus is okay.  I'm a bit stumped.  Approach 1 would be to assume it is a signal integrity issue and take out the scope and check the signals, the power supplies, bypassing, the terminations, etc.  Approach 2 would be to assume it is a logical issue and do more experiments with the addresses you are accessing to see if you can find a specific pattern that leads to the problem.   Do simulations pass?  You could try a little of each debug approach.  Sorry I'm not much help here.

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