12-03-2012 01:49 AM
I have a design in EDK for an ML605 board. When I run the design through ISE I get a message about ddr_parity. It says that it will add a port and connect it an FPGA pin. But I dont need this signal so why is it doing that?
02-20-2013 09:32 AM
Did you ever resolve this? I'm seeing the same behavior with Xilinx ISE/XPS 14.4 when implementing a design for the ML605. I don't really like having randomly assigned pins in my design.
After some investigation, it appears that an OBUF is being instantiated in file phy_control_io.v, line 1,297. I don't think a 204-pin SODIMM socket has a parity pin, so I'm not sure what to do with it. Assign it to an unused FPGA pin for now, perhaps?
06-30-2014 04:56 AM
I have the same issue; as the ddr_parity pin is automatically generated from the MIG program, there does not seem to be a way to stop it from being mapped on one of the external FPGA pins.
Does anybody have a solution for this?