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Scholar beandigital
Scholar
3,435 Views
Registered: ‎04-27-2010

ML605 ddr_parity signal

I have a design in EDK for an ML605 board. When I run the design through ISE I get a message about ddr_parity. It says that it will add a port and connect it an FPGA pin. But I dont need this signal so why is it doing that?

 

Thanks

 

Jon

 

 

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3 Replies
Explorer
Explorer
3,396 Views
Registered: ‎04-09-2008

Re: ML605 ddr_parity signal

Jon,

 

Did you ever resolve this? I'm seeing the same behavior with Xilinx ISE/XPS 14.4 when implementing a design for the ML605. I don't really like having randomly assigned pins in my design.

 

After some investigation, it appears that an OBUF is being instantiated in file phy_control_io.v, line 1,297. I don't think a 204-pin SODIMM socket has a parity pin, so I'm not sure what to do with it. Assign it to an unused FPGA pin for now, perhaps?

 

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Adventurer
Adventurer
2,745 Views
Registered: ‎03-16-2010

Re: ML605 ddr_parity signal

I have the same issue; as the ddr_parity pin is automatically generated from the MIG program, there does not seem to be a way to stop it from being mapped on one of the external FPGA pins.

 

Does anybody have a solution for this?

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Highlighted
1,735 Views
Registered: ‎03-24-2011

Re: ML605 ddr_parity signal

Hy,

we have the same probleme,

have you a solution for this;

 

best regards

Torsten

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