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Observer aruni
Registered: ‎06-07-2011

MMCM Usage

Hello Xilinx Community,



I am working on a design using an MMCM I have instantiated in a pcore. I need a little help, but first let me give some background.



The pcore is fed a 200MHz clock in. This clock drives an instantiated MMCM, which generates 3 output clocks:


1. 480 MHz Varphase, connected to a BUFIO (driving ISERDES)

2. 480 MHz 0deg, connected to logic after the ISERDES - on a BUFG

3. 240 MHz 0deg, connected to further logic - on a BUFG


I am using the clock alignment machine from XAPP881 to align the IO Clock network to the Global clock network.

Data is sampled in the ISERDES, then goes to logic driven by the 480MHz, then to logic by the 240MHZ clock. Since the 480 and 240 are phase aligned, I can directly use the logic in the 240 network without TIG or async fifo.



I wish to use this data in the original 200MHz (or 100MHz) domain. Right now, we are using an asynchronous FIFO to do this task, which was generated in Coregen. However I would like to get away from this.


The simple way is to timing ignore the signals. However, AFAIK we are not, technically speaking, cross clock domain since our clocks are generated from the same reference clock (correct?). When I try to use the 240MHz signal as input to registered logic clocked at 200MHz, I get timing errors such as "Component delays alone exceed constraint" (without the TIG).



Reading the Virtex-6 Clocking Resources Guide (I am using an ML605) I see that an MMCM can be used to create output clocks that do have a phase relationship to the input clock by using a BUFG in the feedback path. My question is, can I do this, and how do I do it? I am a bit confused on how to configure the device to do this (generics/parameters).


I am almost 100% sure that this issue is with the clocks and not with the logic.


If anyone has any insight on how to do this, your help is much appreciated.


Thanks in advance.

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Observer aruni
Registered: ‎06-07-2011

Re: MMCM Usage

Still struggling with this, could really use some help...


Was I clear enough in my question?


I know there are some Xilinx gods out there....






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