UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
4,947 Views
Registered: ‎01-25-2008

MPMC InitDone not going high after reset, but fine during debug..

Jump to solution

Hi,

I have seen similar posts on this topic, but no answers: http://forums.xilinx.com/t5/Embedded-Processing/Issue-accessing-DDR-MPMC-access-via-PowerPC-PLB/m-p/75140#M2949

 

I have a board with a known working design, except that configuration has changed to Master SelectMAP, from Master Serial mode in this design revision.

 

I power up the board, the FPGA configures, DONE=High, all the outputs from the system apear good.

 

The CPU starts executing code in BlockRAM, however I can't bootload into DDR because MPMC_InitDone = Low.

 

If I download code using xmd, and have the "system reset" option selected, the InitDone pin comes high and the system works.

 

My question is what would stop the MPMC_InitDone signal going high (and staying low) after configuration, but then works fine during a normal code download / debug with XMD.??

 

Thanks.

Lachlan Grogan
CEO, SIL3 Pty Ltd
Melbourne, Australia
http://sil3.com.au
0 Kudos
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
6,207 Views
Registered: ‎07-30-2007

Re: MPMC InitDone not going high after reset, but fine during debug..

Jump to solution

For your design, it sounds like you are running into power supply ramping issues.  Are any of your memory voltage rails created by passive voltage dividers? Also make sure that you are not skipping init for simulation in your MPMC MHS.

0 Kudos
5 Replies
Xilinx Employee
Xilinx Employee
6,208 Views
Registered: ‎07-30-2007

Re: MPMC InitDone not going high after reset, but fine during debug..

Jump to solution

For your design, it sounds like you are running into power supply ramping issues.  Are any of your memory voltage rails created by passive voltage dividers? Also make sure that you are not skipping init for simulation in your MPMC MHS.

0 Kudos
Xilinx Employee
Xilinx Employee
4,939 Views
Registered: ‎07-30-2007

Re: MPMC InitDone not going high after reset, but fine during debug..

Jump to solution
Another common issue not directly related to this is that the UNUSEDPIN bitgen setting puts pulldowns on unused pins- such as VREF pins with only output pins in the bank.

I hope this helps,
Dylan
0 Kudos
Explorer
Explorer
4,931 Views
Registered: ‎01-25-2008

Re: MPMC InitDone not going high after reset, but fine during debug..

Jump to solution

Hi Dylan.

 

1.  The board is powered up and I am either downloading the bit stream to the FPGA, or loading the PROM.  I did this to rule out PSU sequencing.  I must stress that this design has been working for a long time now, and I have just made some minor changes to the IP Cores, the board layouts, etc are known to work.

2.  The design has worked in the past, the only difference is the SelectMAP interface to the PROM.

3.  Sim init is not skipped, and I have tested on both MPMC4.03 and MPMC5.04 with the same results.

4.  I am watching the output of the reset controller and I get a 50uS long pulse after configuration.  This demonstrates that the reset controller is working just fine.  THe firmware in BRAM executes, but can't access DDR until its available.

5.  Immediatly after configuration, MPMC_InitDone stays low, until the board gets a second reset.

6.  Memory rails are powered by regulators and have been checked for tolerance.

7.  I have set the Unused Pin options to PullUp, and Pull none without any effect.

 

Do you have any suggestions:??  Really at wits end with this one...

 

Cheers

Lachlan.

 

 

 

 

 

Lachlan Grogan
CEO, SIL3 Pty Ltd
Melbourne, Australia
http://sil3.com.au
0 Kudos
Explorer
Explorer
4,926 Views
Registered: ‎01-25-2008

Re: MPMC InitDone not going high after reset, but fine during debug..

Jump to solution

Hi Dylan,

I can not thank you enough for your hints...  I have solved the problem, and here is what I have found (For the benefit of others with the same problem).

 

Firstly my system:

I have a V4FX20 connected to dual 256mBit DDR's.  The DDR's run from 2.5V, and I have a TI TPS731125 LDO regulator which supplies the VREF voltage for the DDR's as well as the VREF into the correct locations for each bank in the FPGA.

 

The Problem:

I also had a resistor to ground on the HSWAPEN (Hot Swap Enable) pins.  Although the description of the HSWAPEN is a bit vague, it really should be called N_HSWAPEN, as grounding the signal enables the pullups for the ports during configuration.

 

What was happening is that when the FPGA is powered, and there is an edge on INIT_B the HotSwap system comes into effect and pulls up all of the VREF pins on the banks of the FPGA to 2.5V.  Thus driving 2.5V (via pullup resistors) directly into the little LDO regulator supplying 1.25V.  The 1.25V line is raised somewhere to about 1.8V.  After the configuration has finished, the pins return to normal and the voltage regulator recovers (possibly thermal recovery).  The recovery takes a few hundred ms, however during this time the MPMC has already failed its calibration and hence I do not get a MPMC_InitDone after configuration.  If I manually reset the system (using XMD) then the 1.25V has already stabilised and I get the MPMC_InitDone at the correct time.

 

Thanks again for your help.

Regards.

Lachlan.

 

Lachlan Grogan
CEO, SIL3 Pty Ltd
Melbourne, Australia
http://sil3.com.au
0 Kudos
Observer wen119at
Observer
4,566 Views
Registered: ‎02-16-2010

Re: MPMC InitDone not going high after reset, but fine during debug..

Jump to solution

Hi Dylan,

 

Can you please help me with my InitDone problem? Many thanks.

http://forums.xilinx.com/t5/Embedded-Processing/sos-Problem-with-MPMC-Clk0-InitDone-remains-LOW/td-p/228505

0 Kudos