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Contributor
Contributor
5,906 Views
Registered: ‎09-17-2008

Maximum frequency for Spartan-3A dsp speedgrade -4

I am working on a project with this Spartan chip and I am currently using a 32MHz clock as input to a DCM and the output from the DCM is 64MHz. This does not invoke any constraint problems, but looking in the timing report I stumble on something.

Looking at timing score:

------------------------------------------------------------------------------------------------------
  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing  
                                            |         |    Slack   | Achievable | Errors |    Score  
------------------------------------------------------------------------------------------------------
  TS_clock_generator_0_clock_generator_0_DC | SETUP   |     0.126ns|    15.499ns|       0|           0
  M0_CLK_OUT_5_ = PERIOD TIMEGRP         "c | HOLD    |     0.494ns|            |       0|           0
  lock_generator_0_clock_generator_0_DCM0_C |         |            |            |        |           
  LK_OUT_5_" TS_sys_clk_pin /         2 HIG |         |            |            |        |           
  H 50%                                     |         |            |            |        |           
------------------------------------------------------------------------------------------------------
  TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | SETUP   |    29.279ns|     1.971ns|       0|           0
  pin" 31.25 ns HIGH 50%                    | HOLD    |     0.929ns|            |       0|           0
------------------------------------------------------------------------------------------------------

 

I see that the "best case achievable" is 15.499ns. This equals to 64.52MHz. So I guess this is the maximum frequency that this clock can achieve.

Looking furtherdown in the timing report I find:

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_sys_clk_pin                 |     31.250ns|      1.971ns|     30.998ns|            0|            0|            4|      1809360|
| TS_clock_generator_0_clock_gen|     15.625ns|     15.499ns|          N/A|            0|            0|      1809360|            0|
| erator_0_DCM0_CLK_OUT_5_      |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

 

This tells me that the requirements is 15.625ns (=64MHz) and that the actual period is the exact same as the maximum period = 15.499ns.

 

So first of all I think its a bit weird that the maximum frequency of the clock is the exact same as the actual period achieved.

And secondly I thought that the Spartan-3A DSP speedgrade -4 should be able to go faster than approx 64MHz.

Some thing I understood wrong here?

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5 Replies
Historian
Historian
5,894 Views
Registered: ‎02-25-2008

Re: Maximum frequency for Spartan-3A dsp speedgrade -4

The tools work to achieve your given period timing constraint. They will not try to over-do it. If you set a 64 MHz clock frequency constraint, the tools will not keep working to give you a 100 MHz result.

 

Which, I suppose, is the whole point of the period timing constraint. Why do more than necessary?

 

If you wanted the design to run at 100 MHz, change your period constraint and re-run the tools. You can probably expect the tools run-time to increase as they do more "stuff" to meet the requirement.

 

-a

----------------------------Yes, I do this for a living.
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Contributor
Contributor
5,873 Views
Registered: ‎09-17-2008

Re: Maximum frequency for Spartan-3A dsp speedgrade -4

That seems to make sense. But then I have another question.

I tried to change the frequency from 64MHz to 96MHz but that gave me a timing constraint error.I thought that the Spartan-3A DSP could go 96MHz.

Any good guides to understand the origin of timing errors and how to fix them?

 

 

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Historian
Historian
5,802 Views
Registered: ‎02-25-2008

Re: Maximum frequency for Spartan-3A dsp speedgrade -4


onklen wrote:

That seems to make sense. But then I have another question.

I tried to change the frequency from 64MHz to 96MHz but that gave me a timing constraint error.I thought that the Spartan-3A DSP could go 96MHz.

Any good guides to understand the origin of timing errors and how to fix them?

 

 


The chip should go that fast. The question is whether your code has lots of combinatorial logic between the flops.

 

-a

----------------------------Yes, I do this for a living.
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Contributor
Contributor
5,734 Views
Registered: ‎09-17-2008

Re: Maximum frequency for Spartan-3A dsp speedgrade -4

I have been looking at the timing report again and this is what it looks like.

What I can understand from this is that the path for the clock to the BRAM is so long that the slack becomes negative. 

So my question is what I can do to fix this? Can I change the requirements or do someething else to re-route it?

Any help is most appreciated.

 

--------------------------------------------------------------------------------
Release 10.1.03 Trace  (nt)
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.

trce -e 3 -xml system.twx system.ncd system.pcf

Design file:              system.ncd
Physical constraint file: system.pcf
Device,package,speed:     xc3sd3400a,fg676,-4 (PRODUCTION 1.33 2008-07-25)
Report level:             error report

Environment Variable      Effect
--------------------      ------
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
   a 50 Ohm transmission line loading model.  For the details of this model,
   and for more information on accounting for different loading conditions,
   please see the device datasheet.

================================================================================
Timing constraint: TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_pin" 31.25 ns HIGH
50%;

 4 paths analyzed, 4 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is   2.144ns.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_clock_generator_0_clock_generator_0_DCM0_CLK_OUT_7_ =
PERIOD TIMEGRP         "clock_generator_0_clock_generator_0_DCM0_CLK_OUT_7_"
TS_sys_clk_pin /         3 HIGH 50%;

 1003207 paths analyzed, 26288 endpoints analyzed, 3539 failing endpoints
 3539 timing errors detected. (3539 setup errors, 0 hold errors)
 Minimum period is  20.076ns.
--------------------------------------------------------------------------------
Slack:                  -9.660ns (requirement - (data path - clock path skew + uncertainty))
  Source:               microblaze_0/microblaze_0/Area.Decode_I/PreFetch_Buffer_I/Using_FPGA.Buffer_DFFs[1].FDS_I (FF)
  Destination:          masterbram2/masterbram2/ramb16bwer_30 (RAM)
  Requirement:          10.416ns
  Data Path Delay:      20.074ns (Levels of Logic = 4)
  Clock Path Skew:      -0.002ns (0.595 - 0.597)
  Source Clock:         dlmb_cntrl_1_BRAM_PORT_BRAM_Clk rising at 0.000ns
  Destination Clock:    dlmb_cntrl_1_BRAM_PORT_BRAM_Clk rising at 10.416ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: microblaze_0/microblaze_0/Area.Decode_I/PreFetch_Buffer_I/Using_FPGA.Buffer_DFFs[1].FDS_I to masterbram2/masterbram2/ramb16bwer_30
    Delay type         Delay(ns)  Logical Resource(s)
    ----------------------------  -------------------
    Tcko                  0.580   microblaze_0/microblaze_0/Area.Decode_I/PreFetch_Buffer_I/Using_FPGA.Buffer_DFFs[1].FDS_I
    net (fanout=67)       1.935   microblaze_0/microblaze_0/buffer_Addr<1>
    Tilo                  0.692   microblaze_0/microblaze_0/Area.Decode_I/PC_Incr_0_and00001
    net (fanout=1)        0.963   microblaze_0/microblaze_0/pc_Incr
    Topcyg                1.178   microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[29].PC_Bit_I/SUM_I
                                  microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[29].PC_Bit_I/MUXCY_X
    net (fanout=1)        0.000   microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[29].PC_Bit_I/MUXCY_X/O
    Tciny                 0.864   microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[28].PC_Bit_I/MUXCY_X
                                  microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[27].PC_Bit_I/XOR_X
    net (fanout=1)        0.762   microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[27].PC_Bit_I/pc_Sum
    Tilo                  0.707   microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[27].PC_Bit_I/NewPC_Mux
    net (fanout=65)      11.933   ilmb_port_BRAM_Addr<27>
    Trcck_ADDRA           0.460   masterbram2/masterbram2/ramb16bwer_30
    ----------------------------  ---------------------------
    Total                20.074ns (4.481ns logic, 15.593ns route)
                                  (22.3% logic, 77.7% route)

--------------------------------------------------------------------------------
Slack:                  -9.269ns (requirement - (data path - clock path skew + uncertainty))
  Source:               microblaze_0/microblaze_0/Area.Decode_I/PreFetch_Buffer_I/Using_FPGA.Buffer_DFFs[1].FDS_I (FF)
  Destination:          masterbram2/masterbram2/ramb16bwer_30 (RAM)
  Requirement:          10.416ns
  Data Path Delay:      19.683ns (Levels of Logic = 4)
  Clock Path Skew:      -0.002ns (0.595 - 0.597)
  Source Clock:         dlmb_cntrl_1_BRAM_PORT_BRAM_Clk rising at 0.000ns
  Destination Clock:    dlmb_cntrl_1_BRAM_PORT_BRAM_Clk rising at 10.416ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: microblaze_0/microblaze_0/Area.Decode_I/PreFetch_Buffer_I/Using_FPGA.Buffer_DFFs[1].FDS_I to masterbram2/masterbram2/ramb16bwer_30
    Delay type         Delay(ns)  Logical Resource(s)
    ----------------------------  -------------------
    Tcko                  0.580   microblaze_0/microblaze_0/Area.Decode_I/PreFetch_Buffer_I/Using_FPGA.Buffer_DFFs[1].FDS_I
    net (fanout=67)       1.935   microblaze_0/microblaze_0/buffer_Addr<1>
    Tilo                  0.692   microblaze_0/microblaze_0/Area.Decode_I/PC_Incr_0_and00001
    net (fanout=1)        0.963   microblaze_0/microblaze_0/pc_Incr
    Topcyg                0.787   microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[29].PC_Bit_I/MUXCY_X
    net (fanout=1)        0.000   microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[29].PC_Bit_I/MUXCY_X/O
    Tciny                 0.864   microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[28].PC_Bit_I/MUXCY_X
                                  microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[27].PC_Bit_I/XOR_X
    net (fanout=1)        0.762   microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[27].PC_Bit_I/pc_Sum
    Tilo                  0.707   microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[27].PC_Bit_I/NewPC_Mux
    net (fanout=65)      11.933   ilmb_port_BRAM_Addr<27>
    Trcck_ADDRA           0.460   masterbram2/masterbram2/ramb16bwer_30
    ----------------------------  ---------------------------
    Total                19.683ns (4.090ns logic, 15.593ns route)
                                  (20.8% logic, 79.2% route)

--------------------------------------------------------------------------------
Slack:                  -8.953ns (requirement - (data path - clock path skew + uncertainty))
  Source:               microblaze_0/microblaze_0/Area.Data_Flow_I/Operand_Select_I/Using_FPGA.OpSelect_Bits[0].Operand_Select_Bit_I/Op1_Reg_DFF (FF)
  Destination:          masterbram2/masterbram2/ramb16bwer_30 (RAM)
  Requirement:          10.416ns
  Data Path Delay:      19.289ns (Levels of Logic = 4)
  Clock Path Skew:      -0.080ns (0.595 - 0.675)
  Source Clock:         dlmb_cntrl_1_BRAM_PORT_BRAM_Clk rising at 0.000ns
  Destination Clock:    dlmb_cntrl_1_BRAM_PORT_BRAM_Clk rising at 10.416ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: microblaze_0/microblaze_0/Area.Data_Flow_I/Operand_Select_I/Using_FPGA.OpSelect_Bits[0].Operand_Select_Bit_I/Op1_Reg_DFF to masterbram2/masterbram2/ramb16bwer_30
    Delay type         Delay(ns)  Logical Resource(s)
    ----------------------------  -------------------
    Tcko                  0.676   microblaze_0/microblaze_0/Area.Data_Flow_I/Operand_Select_I/Using_FPGA.OpSelect_Bits[0].Operand_Select_Bit_I/Op1_Reg_DFF
    net (fanout=8)        1.250   fsl_v20_m_s_FSL_M_Data<0>
    Tilo                  0.707   microblaze_0/microblaze_0/Area.Decode_I/Using_FPGA.force_di1_LUT3
    net (fanout=1)        1.186   microblaze_0/microblaze_0/Area.Decode_I/force_DI1
    Topcyg                0.787   microblaze_0/microblaze_0/Area.Decode_I/Using_FPGA.MUXCY_JUMP_CARRY
    net (fanout=1)        0.000   microblaze_0/microblaze_0/Area.Decode_I/Using_FPGA.MUXCY_JUMP_CARRY/O
    Tbyp                  0.130   microblaze_0/microblaze_0/Area.Decode_I/Using_FPGA.MUXCY_JUMP_CARRY2
                                  microblaze_0/microblaze_0/Area.Decode_I/Using_FPGA.MUXCY_JUMP_CARRY3
    net (fanout=46)       1.453   microblaze_0/microblaze_0/Area.Decode_I/Using_FPGA.MUXCY_JUMP_CARRY3/O
    Tilo                  0.707   microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[27].PC_Bit_I/NewPC_Mux
    net (fanout=65)      11.933   ilmb_port_BRAM_Addr<27>
    Trcck_ADDRA           0.460   masterbram2/masterbram2/ramb16bwer_30
    ----------------------------  ---------------------------
    Total                19.289ns (3.467ns logic, 15.822ns route)
                                  (18.0% logic, 82.0% route)

--------------------------------------------------------------------------------


Derived Constraint Report
Derived Constraints for TS_sys_clk_pin
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_sys_clk_pin                 |     31.250ns|      2.144ns|     60.228ns|            0|         3539|            4|      1003207|
| TS_clock_generator_0_clock_gen|     10.417ns|     20.076ns|          N/A|         3539|            0|      1003207|            0|
| erator_0_DCM0_CLK_OUT_7_      |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

1 constraint not met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock sys_clk_pin
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
sys_clk_pin    |   20.076|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 3539  Score: 5556176

Constraints cover 1003211 paths, 0 nets, and 43269 connections

Design statistics:
   Minimum period:  20.076ns   (Maximum frequency:  49.811MHz)


Analysis completed Fri Mar 13 10:03:55 2009
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings

Peak Memory Usage: 322 MB


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Xilinx Employee
Xilinx Employee
5,721 Views
Registered: ‎08-06-2007

Re: Maximum frequency for Spartan-3A dsp speedgrade -4

Hi,

 

The fanout for the ilmb_port_BRAM_Addr seems very high.

How much memory do you have one LMB? 128kbyte?

 

I would suggest reducing some and put them on PLB or start using the caches.

 

Routing to 64 BRAM will more or less require a route all around the device which causes a very long routing delay.

 

Göran

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