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Participant
Participant
4,114 Views
Registered: ‎07-23-2010

Maximum frequency provided by XPS

Hello everybody,

 

I have implemented a basic system with BSB and have attached a custom peripheral. But after compiling everything in XPS, I can see in the report (system.log) that the maximum frequency is only 64.499 MHz:

 

Design statistics:

Minimum period: 15.504ns (Maximum frequency: 64.499MHz)

Maximum path delay from/to any node: 5.706ns

Maximum net delay: 0.838ns

 

The clock is running at 100 MHz, and everything works fine as expected... Shouldn't it give strange results or behave strangely??

 

Thanks in advance!

Alejandro Cristo
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Xilinx Employee
Xilinx Employee
4,097 Views
Registered: ‎08-02-2007

Re: Maximum frequency provided by XPS

Hi,

 

The maximum frequency or the minimum period is determined based on the critical path in the design(slowest path).

 

Can you check what is the maximum frequency of design without the custom IP?

 

Thnx

 

 

 

 

 

 

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Participant
Participant
4,085 Views
Registered: ‎07-23-2010

Re: Maximum frequency provided by XPS

Hello htsvn,

 

I have compiled a new BSB with only SDRAM, UartLite1 and BRAM (64 KB) as peripherals. Bus clock: 100MHz, Processor clock: 400MHz.

 

After compiling the hardware the maximum clock period is about 102 MHz:

 

Design statistics:
Minimum period: 9.754ns (Maximum frequency: 102.522MHz)

 

What may the problem be?

 

Thanks.

Alejandro Cristo
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Xilinx Employee
Xilinx Employee
4,063 Views
Registered: ‎08-02-2007

Re: Maximum frequency provided by XPS

Hi,

 

The input to the design is 100MHz. This goes into a DCM/PLL/MMCM and derives the clocks required for each of your

 

module internally. The frequency reported in the synthesis report is based on how the design got synthesized.

 

Do refer to this link which explains about Maximum Synthesis report of XST

 

http://myfpgablog.blogspot.com/2010/11/understand-maximum-frequency-reporting.html

 

Thnx

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Anonymous
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Re: Maximum frequency provided by XPS

 

Hello,

I have a virte-5 FPGA (XC5VLX50T), and I want to increase clock frequency of embedded system includded micriblaze, LEDs, etc up to 400 MHz.

It works right when the frequency is less than 200 MHZ, but when I choose frequency about 300-400 MHz by clockgenerator or PLL, it failes.

and gives an error like this:

----------------------------------------------------------------

ERROR: 1 constraint not met.

PAR could not meet all timing constraints. A bitstream will not be generated.

To disable the PAR timing check:

1> Disable the "Treat timing closure failure as error" option from the Project Options dialog in XPS.

OR

2> Type following at the XPS prompt:
XPS1set enable_par_timing_error 0
********************************************************************************
make: *** [implementation/system.bit] Error 1

----------------------------------------------------------------

When I disable the "Treat timing closure failure as error" option, my design doesn't work.

and I know my FPGA supports frequencies up to 500 MHz as it's mentioned in Virtex-5 datasheet.

I need 300 or 400MHz in my embedded system. how can I solve this problem?

 

Thank you!

 

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