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Observer jwoithe
Observer
4,157 Views
Registered: ‎09-28-2008

Meaning of MDT errors: unknown lane orientation, floating bus interfaces and address generator failures

I have encountered some strange and seemingly undocumented errors while using EDK 10.1 SP3.  By way of background, I have implemented a locallink switch IP which switches the locallink interface of a TEMAC on a virtex4 between a xps_ll_fifo IPcore and a custom core.  All this works very well.  However, every so often EDK reports

 

WARNING:MDT - Unknown lane orientation _BK______|________

This message comes in threes.  Does anyone have an idea of what this is indicating?  I'm happy to just ignore it since things work fine, but at the same time it must mean something, right?

 

The afore-mentioned custom core also implements a XIL_BRAM bus interface which I connect to port B of a standard dual-port BRAM IPcore block in the design.  Without the connection being made EDK successfully constructs a block diagram of the project.  If I make the BRAM bus connection however, attempts to create a block diagram result in an incomplete diagram, with the following messages reported by EDK:

WARNING:MDT - Memory controller TriMode_MAC_GMII has a floating bus interface connected to bus TriMode_MAC_GMII_LLINK0 that should be connected to a processor.

There are 6 of these - one for each end of the locallink buses I have in the design.  The design still works as expected but again this message must mean something.  Any ideas?

 

Finally, with the BRAM bus still connected I find the address generator no longer works:

ERROR:MDT - Address Generator cannot generate addresses for your design. Please provide the address manually.

Any ideas as to what causes the address generator to fail like this?

 

Any suggestions about these errors/warnings would be appreciated.  I've searched the internet extensively and have not found anything in connection with these messages.

 

Regards

  jonathan

 

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3 Replies
Observer jwoithe
Observer
4,126 Views
Registered: ‎09-28-2008

Re: Meaning of MDT errors: unknown lane orientation, floating bus interfaces and address generator failures

I take it that no one knows what these warning/error messages mean.  Are there any documents in existence which describe the various "MDT" messages?  If there are I'd gladly look them up if you can tell me where to find them - I've got no joy from the search engines.

 

Failing that, how else does one discover what these particular warnings are trying to say?

 

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Xilinx Employee
Xilinx Employee
4,103 Views
Registered: ‎05-31-2009

Re: Meaning of MDT errors: unknown lane orientation, floating bus interfaces and address generator failures

Hi,

 

Please send me your MHS of AddrGen failing, jibinh@xilinx.com. Please do include the local pcores.

 

Thanks,

Jibin

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Observer jwoithe
Observer
4,090 Views
Registered: ‎09-28-2008

Re: Meaning of MDT errors: unknown lane orientation, floating bus interfaces and address generator failures

I have sent you the files as requested.  Please let me know if there is anything else I can provide which will help identify the meaning of these warnings and errors.

 

Jonathan

 

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