11-27-2013 07:53 AM
Hi all,
We have upgraded to vivado 2013.3 from Planahead 14.5. I decided to give a try to the "Block design" for my Microblaze system instantiation. Everything was working fine in my local test project (synthesis/implementation/bitstream and export to SDK...) .
Then comes the time to merge my "Block design" to the main project. I copied the "/bd/" folder to the main project and use the regular "Add Sources" menu and "Existing block design" option.
The block design is there, but after synthesis/implementation of the main project ,there is this error :
[Memdata 28-96] Could not find a BMM_INFO_DESIGN property in the design. Could not generate the merged BMM file.
And this Critical Warning :
[Memdata 28-122] data2mem failed with a parsing error. Check the bmm file or the bmm_info_* properties on the BRAM components. The design BRAM components initialization strings have not been updated.
Thoses errors doens't help at all since there is 90 block rams in the projects from 4 different peoples.
I just want to make sure my part (the block design) is fine.
Both , the main project and my local project are fine separatly.
I tried to re-Generate Block Design from the main project.
I tried to manually add the BMM I found in the /bd/ folder with the "Add source" button.
I tried resetting all the runs and re-synthesis/implementation.
Any help is greatly appreciated!
Thx
11-27-2013 10:40 PM
Hi,
This is a known issue, and a change request has been filed for this issue.
This is due to a label being used with the generate statement. For example:
generate
//if(PIPE_SIM_MODE == "FALSE") begin //This works
vs.
if(PIPE_SIM_MODE == "FALSE") begin : gt_top // This doesn't work
Remove the label and check.
Regards,
11-28-2013 08:26 AM
You are right,
I removed the generate and that solved the problem.
Thx!
11-28-2013 09:28 AM
Hi,
Please mark "Accept as solution" if the information provided was helpful.
Regards,
02-13-2014 05:08 AM
Hi,
we have the same issue, but all of our block RAM etc is generated from vivado IP.
It is a simple microblaze project on an Artix 7 100T device.
I cannot see where I can remove any label.
Please let me know if there is any other workaround for this issue as it is stopping our development.
Thank you
03-31-2014 05:18 AM
03-31-2014 12:01 PM
04-01-2014 11:15 PM
I have similar trouble with IP component 'microblaze_mcs' instance. Renaming IP does not help. There is detailed problem description : I am using AC701 board for my experiments as prototype. My design contains instance of 'microblaze_mcs' IP. There is small standalone software, I build it using SDK, it starts well under SDK enviroment. But when I am trying to initialize ROM in my Vivado project I get to cases : 1. If I added only ELF file to proect (and associate it to MCS instance, of course) all necessary implementation steps (including bitstream generation) completed successfully, but my software (already debugged using SDK) actually does not start in hardware. It seems to me that BRAMs stays blank, so no code could be started. 2. If I added 'system_bd.bmm' file to my project (to tell Vivado software that design contains some ROMs and it is necessary to update their locations after routing stage) - I get the same error as described earlier :
[Memdata 28-96] Could not find a BMM_INFO_DESIGN property in the design. Could not generate the merged BMM file.
My question is : how to fix this problem?
Regards,
Jury
03-23-2015 05:41 AM
Hello All,
Can somebody please help on this issue regarding the failure in generating BMM file. My design is realized on Microzed board on Vivado 2014.3.1. The bitstream file is generated but the error comes as well. Is this error harmful?
I could also not find where to find this generate statement? which file?????
Anyone??? achutha
08-17-2015 11:30 AM
I'm getting this error with vivado 2015.2
so it looks like it still hasn't been fixed, but the strange thing is the bit file works fine so it
looks like a false error;
08-17-2015 12:30 PM
Hey guys. This issue can be seen under the following conditions:
the string 'microblaze' is used as the bd name
bd is added as OOC / DCP / netlist /edif file
if the bram controller is connected to an external bram
if a custom IP contestingif memory with a bram interface is connected to bram controller
if the microblaze_0_local_memory is renamed
if there is an IP between the bram controller and bram
if you have any of the set ups below let me know and I'll post a script to workaround this
08-25-2015 03:27 AM
08-26-2015 07:40 AM
Hey,
Can you comment of you have one of the set-ups seen in my previous thread. this issue can occur for a number of reason. Can you describe your project?
09-02-2015 01:19 AM
Hi Stephen,
I've a design where I'm seeing this (in 2015.2). You've identified 6 possible causes:
I've fixed (1) and (5). I never had (3), (4) or (6).
That leaves (2). I am importing the microblaze processor system as a DCP (built with an older Vivado version that understands XMP / MHS files).
I've tried various manual assigments of BMM_INFO_DESIGN and use of write_bmm with no joy.
Do you have any suggestions for working around (2)?
Thanks!
09-07-2015 02:37 PM - edited 09-09-2015 05:55 AM
03-09-2017 07:10 AM
Hey all,
I have a similar problem described here:
Is there anything you can suggest?
Thank you
Vlad
06-13-2017 01:33 AM
Hi
I'm getting this error in Vivado 2017.1 doing the advance embedded tutorial for Zynq lab 4. Even though it shows the error message, the bit file is generated so can I assume it's a false flag?
Thank you
01-14-2019 07:11 PM
hello, I have the "if the bram controller is connected to an external bram", and get the error 28-96.
How can I fix it?
04-07-2019 11:55 PM
I'm getting the above error and i have the situation "if a custom IP contestingif memory with a bram interface is connected to bram controller" How can i solve?
thank you