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tkontogiorgis
Explorer
Explorer
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Registered: ‎09-10-2019

Memory Read Error at adress. EDITR overrun

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Hello,

I am using XilinxSDK 2019.1. I am implementing a custom IP with AXI-4 Lite interface. I am trying to read a register (i.e Register0 which is the Base Adress of the IP) from XSCT console and i am having this error :

Memory read error at 0xA0040000. EDITR overrun

This register is in stable state not written or readen somewhere else, so i assume this error shouldnt exist..

Any thoughts or suggestions?

Thanks,

Theo

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tkontogiorgis
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Explorer
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Registered: ‎09-10-2019

Hi @ibaie ,

seems that maybe i found the problem. Because my AXI interface has low frequency i needed to lower the JTAG frequency of hw_server. The same was done when i triggered the ILA via Vivado. The solution was proposed in the post you mentionted.

Thanks for support,

Theo

View solution in original post

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tkontogiorgis
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Explorer
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Registered: ‎09-10-2019

Hello,

Any thoughts please?

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tkontogiorgis
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Explorer
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Registered: ‎09-10-2019

Hello,

Any recommendations please?

Theo

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ibaie
Xilinx Employee
Xilinx Employee
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Registered: ‎10-06-2016

Hi @tkontogiorgis 

I would suggest to place a debug core ILA in the AXI interconnect to check whether the transaction is happening or not. It is also interesting to see from which target in the device are you performing the read operation as XSDB is a context aware debugger.

Regards


Ibai
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tkontogiorgis
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Registered: ‎09-10-2019

Hello @ibaie ,

About " It is also interesting to see from which target in the device are you performing the read operation as XSDB is a context aware debugger" :

I am using only 1 Arm core and targeting this core as seen below:

target.PNG

So is it ok?

Thanks for resonse,

Theo

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ibaie
Xilinx Employee
Xilinx Employee
744 Views
Registered: ‎10-06-2016

Hi @tkontogiorgis 

That's OK, I was just trying to point out that the context does matter when using the debugger. Did you btw test accessing the register from other targets, i.e. R5? Additionally just to isolate the issue to the debugger did you try to access the register from A53 running a test application or so?

Anyway whenever facing AXI transaction issues to an IP the best idea is to add an ILA to the design for debug purposes. It will give you much more visibility on what's going on in the bus.

Regards


Ibai
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tkontogiorgis
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Registered: ‎09-10-2019

Hi @ibaie ,

I just putted ILA probes and the transaction is ok. Something very strange happened, after the ILA was triggered the error dissapeared... I do not understand. Now i can read my custom IP register even if i re-programm it again. Was it maybe some kind of Xilinx SDK bug? 

Thanks,

Theo

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tkontogiorgis
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Registered: ‎09-10-2019

Hi @ibaie ,

Could you advise me in something please? About the read process of axi register i am having this somewhere ( in the writing process after synchronous reset) :

readprc.PNG

Does this continuous assignment in the process maybe affect the read process and the master cannot read because of this?

Thanks

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ibaie
Xilinx Employee
Xilinx Employee
684 Views
Registered: ‎10-06-2016

Hi @tkontogiorgis 

It's strange but there was a previous thread in the forum and they also got the issue disappeared once the ILA was included in the design.

https://forums.xilinx.com/t5/Embedded-Development-Tools/Is-there-a-way-to-lengthen-the-time-out-setting-for-XSDB-XSCT/td-p/940270

To be honest it is going bit out of my expertise on this

Regards


Ibai
Don’t forget to reply, kudo, and accept as solution.
tkontogiorgis
Explorer
Explorer
648 Views
Registered: ‎09-10-2019

Hi @ibaie ,

seems that maybe i found the problem. Because my AXI interface has low frequency i needed to lower the JTAG frequency of hw_server. The same was done when i triggered the ILA via Vivado. The solution was proposed in the post you mentionted.

Thanks for support,

Theo

View solution in original post

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