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sridar-s
Adventurer
Adventurer
1,191 Views
Registered: ‎01-09-2011

Memory update issue

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I am trying to create the simple AXI Master in PL and interfaced to S_AXI_HP1_FPD port on Zynq XCZU9EG device. The software code on SDK is a very basic one to continuously read the data on the target memory address locations. I don't see the updated values on memory locations in the software unless I exit the debug session and re-run the code. It's the same behavior on memory window as well. Any help on this ?

 

P.S. I use ZCU102 Eval board with Vivado 2017.4.

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stephenm
Xilinx Employee
Xilinx Employee
1,389 Views
Registered: ‎09-12-2007
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stephenm
Xilinx Employee
Xilinx Employee
1,390 Views
Registered: ‎09-12-2007
sridar-s
Adventurer
Adventurer
1,151 Views
Registered: ‎01-09-2011

It worked! Thanks.

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stephenm
Xilinx Employee
Xilinx Employee
1,135 Views
Registered: ‎09-12-2007
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