UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
378 Views
Registered: ‎08-11-2019

MicroBlaze is under reset while running sdk

please help me how to fix attached file error

sdk_error.PNG
0 Kudos
7 Replies
Scholar dpaul24
Scholar
368 Views
Registered: ‎08-07-2014

Re: MicroBlaze is under reset while running sdk

harinatha.reddy@eldaas.com,

Did you try the 3 'Troubleshooting Hints' listed? What are the results?

Please post the BD highliting the system reset input. Re-check on your system_reset signal propagation.

Did you forget to de-assert it?

Has it been connected to the recommended FPGA reset pin (re-check your ucf/xdc)?

 

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------
0 Kudos
Explorer
Explorer
346 Views
Registered: ‎12-05-2016

Re: MicroBlaze is under reset while running sdk

 

Hi harinatha.reddy@eldaas.com ,

How you are providing reset to microblaze? If you are directly providing an external reset from the board please check the polarity. 

I also had an experience of getting the same error. That time issue was wrong polarity of reset input to microblaze. 

One method I followed is attached.

Reference link : https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug898-vivado-embedded-design.pdf 

(page - 110) 

Thanks & Regards,

Reshma 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

reset.JPG
0 Kudos
308 Views
Registered: ‎08-11-2019

Re: MicroBlaze is under reset while running sdk

Thamk you for your response, i am using xilinx ise 14.7 not vivado tool

0 Kudos
Moderator
Moderator
246 Views
Registered: ‎10-06-2016

Re: MicroBlaze is under reset while running sdk

Hi harinatha.reddy@eldaas.com 

If I'm not wrong you might have the same error if the Microblaze is not clocked, so could you provide more details about the clock? If the clock is comming from the PS side (on Zynq based devices) you should ensure that the PS is being initialized prior downloading the application to the memory as otherwise the clock is not going to be running.

Regards


Ibai
Don’t forget to reply, kudo, and accept as solution.
0 Kudos
236 Views
Registered: ‎08-11-2019

Re: MicroBlaze is under reset while running sdk

ok thank you for your suggession i will check

0 Kudos
Scholar dpaul24
Scholar
231 Views
Registered: ‎08-07-2014

Re: MicroBlaze is under reset while running sdk

@ibaie,

If I'm not wrong you might have the same error if the Microblaze is not clocked, so could you provide more details about the clock? If the clock is comming from the PS side (on Zynq based devices) you should ensure that the PS is being initialized prior downloading the application to the memory as otherwise the clock is not going to be running.

The OP is using ISE which mean sthat the FPGA under use is a non-zynq part.

harinatha.reddy@eldaas.com,

Again, please check your if the clock is provided and the uBlaze is properly brought out of reset. These basic connections have nothing to do with the Xilinx tool type you are using.

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------
0 Kudos
223 Views
Registered: ‎08-11-2019

Re: MicroBlaze is under reset while running sdk

ok thank you,

i am designing edk design ie, digital input data send to SBC(single board computer) for that i used PCI some cores i have to add can you suggest what i have to add in edk design or any reference designs available share with me

0 Kudos