09-30-2011 09:24 PM
I know I'm doing something dumb, I just don't know what it is...maybe you can help. I have a system that has 2 V5 devices one of which has a Microblaze in it. When I run my system through the 13.2 debugger, (program FPGA, Run) the whole thing works great. I am using the red USB download cable. The system involves communications via a serial port so aliveness is obvious.
Then I take my two V5 bitstreams. I run them through PROM Formatter to generate a image that I download to single SPI PROM. The layout is like this: SPI->V5 with MB->V5. I then take the resulting mcs file and program the SPI PROM (that is attached to the first FPGA that will have the MicroBlaze in it). Then I pulse power to my system and the V5 devices seem to come alive but the MicroBlaze application doesn't start.
What have I done wrong? Where should I look?
10-05-2011 05:54 AM
10-05-2011 07:53 PM
The code is stored in BRAM. I believe the issue is that the bitstream image that includes the code in BRAM has the startup clock set to JTAG. Ordinarily, iMPACT can detect and correct the startup clock to CCLK when creating a PROM file but it does not or cannot do so for some reason for me. I have to get the bitstream regenerated with the startup clock setting corrected.
10-06-2011 05:34 AM
Ahh, yes the old startup clock pain - I changed my flash programming app to check for that after I got stung twice by it :)
You *can* hack the bitstream in a hex editor to fix that if you're feeling brave... (rather than regenerating it)
There's a write to the COR0 register near the beginning of the bitstream which sets the JTAG/CCLK bit bits 16:15 need to be 00 for CCLK (see page 121 of the V5 config userguide).
On page 127 there a sample bitstream - 2/3 of the way down there's a write to COR0 (0x30012001) - find that sequence in your bitstream and hack the 32-bits after it to clear bits 16:15.
(There's probably a way to do this with bitgen, but I was doing it within my embedded app, so raw bit hacking was the way for me :)