I am using a ML605 board and want to build a top level design consisting of a Microblaze processor and a DDR3 interface (generated by MIG). The DDR3 is no peripheral of the Microblaze.
I removed the clock generator which is built into the Microblaze per default and placed a similar one also on top level. It now generates single-ended 200 MHz clock from the differential input on the board and provides it to the Microblaze and the DDR3.
Now the problem: When trying to PAR the design, it is mentioned that the DDR3 interface signals (like app_rdy, app_wdf_data. etc.) have a too high hold time violation ("WARNING:Route:466 - Unusually high hold time violation detected among 117 connections. The top 20 such instances are printed below. The router will continue and try to fix it"). Then, the router works literally for ever trying to fix that issue.
Whereas implementing either the DDR3 or the microblaze in the top level design, the process finishes properly. So, I suppose it's a question of the right clock distribution/buffering. But I can't figure out how to solve this issue.