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Visitor halils
Visitor
784 Views
Registered: ‎07-17-2018

Microblaze held in rest

I am trying to create microblaze for the first time on my Basys3 board. I used board file from Digilent. I exported the project from vivado and select it from SDK. In SDK I used Hello world Project, it build successfully. However, I cannot see the "Hello world" in my terminal( Used linux screen program). In debug mode, I get the "Error while launching program: Cannot stop MicroBlaze. MicroBlaze is held in reset" error.

 

As I investigate, reset button showed up suspicious. I reversed the reset signal in wrapper and the result did not change the error. So, I assumed my error is not the reset.

 

To anyone interested, I am uploading the project here.

https://drive.google.com/open?id=1TV3a9GUCBg-5wpw1T5b2-FX1CLl-Sd2K

 

Also, I am uploading the diagram of the design.

 

Thanks for your help.
 

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1 Reply
Xilinx Employee
Xilinx Employee
755 Views
Registered: ‎02-01-2008

Re: Microblaze held in rest

It looks like a pretty straight forward design and only relies on external differential clk and reset. If you have not added software to the vivado project, then the microblaze would run in a continuous loop that exists in the LMB BRAM by default.

 

So either pin descriptions are off (verify by opening vivado implementation), reset is broken, or clk is not happening.

 

You say you inverted reset in the wrapper. Also check that processor system reset block input axi_reset_in is tied to a 1 by enabling 'pin tie offs' in the IPI settings window (gear in upper right corner of block diagram).

 

If you have chipscope, you could use a VIO core to monitor clk from the clk module, and some of the resets. The VIO core requires a clk so I use the startup block which always has a clk output around 50MHz. You can't use this clk for baudrates but it can get a design running.

 

If not using VIO, try using the startup block instead of the differential input and clk module.

 

I've attached a verilog file that instantiates the startup block. It can be added to the project, and then added to the IPI block as a module. You may have to change the version of startup block depending on what FPGA family is on the Basys3 board. You can use the vivado 'language templates' to view how to instantiate the correct startup block for your device family.

 

 

 

 

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