cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
265 Views
Registered: ‎10-23-2017

Microblaze is holding in reset when running NVMeOF U50 bitfile.

Jump to solution

Has anyone tried the Xilinx nvmeof solution bitfile based on U50?

I have 4 U50 cards. 2 U50 cards(named CardA) run well. NVME client can connect to U50 successfully. But the other 2 U50 cards(named CardB) stuck at the step of stopping the microblaze.

 

I followed the steps of XNVMe-oF Solution User Guide 2.0 in Jtag mode.

In XSDB shell: 

1. connect (successful)

2. fpga -f design_1_wrapper.bit  (successful)

3. ta   (it shows that the Microblaze is in reset)

4. ta 3 (successful)

5. stop (it shows that the Microblaze is in reset and can't stop)

6. rst (it shows that the Microblaze is in reset and can't stop)

Here is the problem.  CardA is working properly as mentioned as the user guide. But the microblaze in CardB is always holding in reset.

Although this is not an open source design, I wonder if I can get some help. So that I can confirm if it's my CardB's hardware issue that I need to do RMA or it is just a design bug.

Many thanks.

Tags (2)
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
132 Views
Registered: ‎06-02-2017

 

The root cause of the issue was finially found out.

The reset signal which is connected to the reset module of the microblaze was assigned to a pin which is left floating because of the absence of a resistor in its circuit. So the captured value of pin inside of the FPGA might be different from board to board and might be changed with the environmnet changes.

So, I would recommend the customers who are going to run this example to pay attention to the time stamp to make sure it's later than 2020/9/15. The lounge will be updated.

View solution in original post

3 Replies
Highlighted
Moderator
Moderator
172 Views
Registered: ‎06-14-2010

Hello yang.liu@avnet.com , 

I can see you've an open SR with WTS (SR#10498944) and an Engineer (@lettertu) is currently working on this issue.

Please update this topic and provide a solution/workaround to this matter, once the SR is completed and closed. This would help other users in the future, with a similar issue.

Thanks in advance and have a nice day.

Kind Regards,
Anatoli Curran,
Xilinx Technical Support
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
133 Views
Registered: ‎06-02-2017

 

The root cause of the issue was finially found out.

The reset signal which is connected to the reset module of the microblaze was assigned to a pin which is left floating because of the absence of a resistor in its circuit. So the captured value of pin inside of the FPGA might be different from board to board and might be changed with the environmnet changes.

So, I would recommend the customers who are going to run this example to pay attention to the time stamp to make sure it's later than 2020/9/15. The lounge will be updated.

View solution in original post

Highlighted
117 Views
Registered: ‎10-23-2017
Thank you Letter. I will wait for the update.
0 Kudos