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Visitor
Visitor
310 Views
Registered: ‎09-09-2020

Missing Driver for Custom IP

Hi,

 

I am trying to learn how to create a custom AXI peripheral using the Vivado IP generator. I have created a simple IP based on the AXI peripheral template that includes several registers that can be written to and read from the software. I was able to package the IP, include it in the broader FPGA design with the processor, and generate the bitstream all okay. However, when I open Vitis and try to create the hardware platform based on the exported FPGA design, the driver file seems to be missing. From what I understand, this file should have automatically been generated since I was using an AXI peripheral template in the IP generator. While in Vitis I included the IP repository folder that contains my custom IP and re scanned the repositories, but when I try to edit the BSP settings, there is no option for the custom driver I expect to be there.

Snip for Xlinx Question.jpg

Not sure this is important, but in the file groups section of the Packaging Steps view in the IP generator, it doesn't say anything about a file for drivers that I have seen referenced in various tutorials and in a document from Xilinx. 

CollinB_0-1599706612552.png

 

Is there a specific file location I can check to ensure that the driver has in fact been generated? Is there a setting I need to apply or a process I need to run to have the driver generated?

 

Thanks,

 

Collin B.

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5 Replies
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Observer
Observer
263 Views
Registered: ‎08-29-2012

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Newbie
Newbie
120 Views
Registered: ‎11-18-2020

I have the same problem in ip fiel group missing software driver. Did you solve this? What comes in mym mind is if webpack version maybe missing this function to create drivers like header and basic c.

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Observer
Observer
110 Views
Registered: ‎09-05-2020

do you update the hardware specification and then build and clean the platform? works for me with the Webpack, but I don't use the generated drivers. I find it far simpler (and more direct) to get the base IP addresses from the Vivado address editor and all the offsets and bit addresses from the hardware header files generated by HLS. Then I define volatile pointers in my code that I can read/write directly. Some might complain that this is bad practice, but it works and Vivado is very good at adding new addresses without changing the existing ones.

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Moderator
Moderator
105 Views
Registered: ‎09-12-2007

Yes, there is a known issue with the makefiles. This is discussed here:

https://www.xilinx.com/support/answers/75527.html

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Newbie
Newbie
103 Views
Registered: ‎11-18-2020

Hi thx for quick reply, yes hardare specification is up to date and ip was build from clean vhdl codes and generated AXI comuunication and its withou warnings or eerors when synthezsized and packaging. I found on internet that its a bug/ problem with new version Vivado 2020.1 even if a I had updated with to 2020.2 maybe they remove it so it does not generate automatically header nad c. file to file group software drivers. In that case they recommend create new custom ip in version 2019.2 and then just go to 2020.1 with that packaged ip in 2019.2 versaion and there that driver should be. So I am going to try that.

Yeah my colleage done that with tcl commands that created headers but i find that it takes more time when i have 7 custom ips. Do you have some manual how to createt it with HLS that header? Thath colleage is not yeat at our company. Thx in advance.

Kind regards Thomas

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