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Participant
Participant
13,077 Views
Registered: ‎10-31-2012

Multi-channel axi dma engine implementation

Hello!

 

How to implement a multi-channel DMA controller in axi_dma_v6_03_a for the two Ethernet controllers axi_ethernet_v3_01_a?

 

I set the following options but nothing happens, additional ports do not appear

PARAMETER C_ENABLE_MULTI_CHANNEL = 1
PARAMETER C_NUM_MM2S_CHANNELS = 2
PARAMETER C_NUM_S2MM_CHANNELS = 2.

 

In the pg021 indicated the possibility but does not specify how to implement ulti-channel dma.

 

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Xilinx Employee
Xilinx Employee
13,071 Views
Registered: ‎08-02-2011

With multi-channel, there is still only one interface, but data is interleaved on that interface using TID and TDEST.

 

See page 74 here:

http://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v6_03_a/pg021_axi_dma.pdf

 

The AXI Stream Spec would also be useful to read.

www.xilinx.com
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Participant
Participant
13,056 Views
Registered: ‎10-31-2012

thanks, but still not enough real examples of implementation multi -channel dma engine
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Visitor
Visitor
12,661 Views
Registered: ‎11-27-2013

Do there are any news about using multichannel DMA for AXI4 Streams?

We couldn't find anything about that feature in the internet and we want to implement it.

There are no examples, no guides and no helpful documentation. Is this feature really verified by xilinx or is it only a "wewanttohaveinfuture-feature".

Where can we find an example (C, Bare-metal,HDL-Project,IPI) using multichannel dma with "axi4 stream interconnect" ? Is a how-To guide available for it? I do not mean the axi4-spec or the axi4 stream ip documentation, and yes I already read the documentation (not very helpful)....

 

Thanks and regards

Martin

multichannel.JPG
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Visitor
Visitor
12,551 Views
Registered: ‎01-08-2013

Is there any progress? We also face the same problem. Don't know how to use multi-channel dma. What's more the device-tree generator seems too old to support multi-chan


@muencma wrote:

Do there are any news about using multichannel DMA for AXI4 Streams?

We couldn't find anything about that feature in the internet and we want to implement it.

There are no examples, no guides and no helpful documentation. Is this feature really verified by xilinx or is it only a "wewanttohaveinfuture-feature".

Where can we find an example (C, Bare-metal,HDL-Project,IPI) using multichannel dma with "axi4 stream interconnect" ? Is a how-To guide available for it? I do not mean the axi4-spec or the axi4 stream ip documentation, and yes I already read the documentation (not very helpful)....

 

Thanks and regards

Martin



nel dma...

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Visitor
Visitor
12,140 Views
Registered: ‎05-08-2014

In Vivado 2014.1, the DMA version is 8.0. There is not yet an updated PG for it that I can find, this is the latest (for 7.1) http://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf

But there is now an exampe code for multi-channel operation, which exists inside the SDK installation folder:

file:///C:/Xilinx/SDK/2014.1/data/embeddedsw/XilinxProcessorIPLib/drivers/axidma_v8_0/examples/xaxidma_multichan_sg_intr.c

I am able to use this example code, with a DMA in multichannel mode with 2 rx and 2 tx channels. You can either hook up M2SS straight to S2MM (with a slight modification to the TDEST from the code), or you can use AXI4-Stream Interconnects and AXI Traffic Generators (in slave-loopback mode) to get the example to work.

 

Here is a screenshot of my block design for example. I am using DMA in SG mode with multichannel support, 4 rx and 4 tx. Interconnect 0 is simply 1 slave, 4 masters, but interconnect 1 has 4 slaves and 1 master, and you must modify the master High TDEST to 3, so all streams go out the single master.

viv1.png

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Observer
Observer
10,988 Views
Registered: ‎10-16-2014

I'm using 2 traffic generators and 2 axi stream interconnects (as it is in your example), but I'm not able to get the example to work.

 

The first packet is sent and received successfully, but when the second packet is sent the RxDone flag remains 0 and the code stalls into the while(RxDone<NUMBER_OF_BDS_TO_TRANSFER) loop.

 

Do you have any idea why the RxInterruptHandler is not able to set the RxDone flag properly? Can you share your code?

 

Thank you.

 

 

Enrico

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Adventurer
Adventurer
7,960 Views
Registered: ‎09-03-2015

Hello guys,

 

I have a question regarding the DMA in Multichannel. First i show you my block design:

 

 

DMA_Block_design.PNG

I have 2 custom IPs where i generate Data for the DMA. My DMA configuration looks so:

 

DMA_Properties.PNG

 

If i run the PS with Linux i can see only one DMA channel in the Device tree:

 

/ {
                amba_pl: amba_pl {
                               #address-cells = <1>;
                               #size-cells = <1>;
                               compatible = "simple-bus";
                               ranges ;
                               axi_dma_0: dma@40400000 {
                                               compatible = "xlnx,axi-dma";
                                               interrupt-parent = <&intc>;
                                               interrupts = <0 29 4>;
                                               reg = <0x40400000 0x10000>;
                                               xlnx,include-sg ;
                                               dma-channel@40400030 {
                                                               compatible = "xlnx,axi-dma-s2mm-channel";
                                                               interrupts = <0 29 4>;
                                                               xlnx,datawidth = <0x20>;
                                                               xlnx,device-id = <0x0>;
                                               };
                               };
                };
};

So my question is why? What did i wrong?

 

My Axi4-Stream Interconnect has the following configuration:

 

Intercon_1.PNG

 

Intercon_2.PNG

 

I set the High TDEST to 1 because i have 2 slaves. But i don't know if its right. I haven't really understood the meaning of Base/High TDest. Maybe the mistake is on the Software side....

 

I hope that someone can help me. Thanks

 

 

 

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Adventurer
Adventurer
7,834 Views
Registered: ‎09-03-2015

if i debug the design and look at the master stream bus form the axi stream interconnect (M00_AXIS), i realize that there is no tready signal form the DMA... What can be the reasons for that? From what does the tready signal from the S_AXIS_S2MM bus depends on?

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Xilinx Employee
Xilinx Employee
7,810 Views
Registered: ‎08-02-2011

I could be wrong, but I don't think the linux driver supports multichannel mode.

 

Tready not going high probably means the DMA never received a request or is hung.

www.xilinx.com
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