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egholm
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10,249 Views
Registered: ‎05-13-2016

Multi-core in BOOT.bif, how to?

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Hi,

 

I have an UltraScale+ MPSoC and is trying to launch my hello-world app's on the two processors after the FSBL. If I stick to either of the processor everything works fine. That is, a "boot.bif" looking like this works:

 

the_ROM_image:

{
[fsbl_config]r5_single
[bootloader]fsbl_r5.elf
[destination_cpu = r5-0]HelloWorldR5.elf
}

 

And similar for the A53 (with FSBL_A53.elf, HelloWorldA53.elf).

 

But if I mix them, or try to launch both HelloWorld's apps, it doesn't work. E.g:

 

the_ROM_image:
{
[fsbl_config]r5_single
[bootloader]fsbl_r5.elf
[destination_cpu = a53-0]HelloWorldA53.elf
}

 

Then I just get a cranky FSBL:

 

Xilinx Zynq MP First Stage Boot Loader
Release 2016.1 May 12 2016 - 14:38:55
Platform: Silicon, Cluster ID 0xC0000100
Running on R5-0 Processor
Processor Initialization Done
================= In Stage 2 ============
SD1 Boot Mode
SD: rc= 0
File name is BOOT.BIN
Multiboot Reg : 0x0
Image Header Table Offset 0x8C0
*****Image Header Table Details********
Boot Gen Ver: 0x1020000
No of Partitions: 0x4
Partition Header Address: 0x260
Partition Present Device: 0x0
Initialization Success
======= In Stage 3, Partition No:1 =======
XFSBL_ERROR_ADDRESS
Partition 1 Load Failed, 0x2E
================= In Stage Err ============
Fsbl Error Status: 0x0

 

 

Why is that? Maybe it's obvious, but then please guide me in the right direction :)

 

BR,

Martin

 

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egholm
Visitor
Visitor
18,495 Views
Registered: ‎05-13-2016

Ok, I will answer myself - just for the record :)

 

The reason was that I was trying to load my A53's app into a DRAM address not available from the R5.

The lower portion of the address space is reserved for addressing the R5's TCM (tightly coupled memory) (as seen from the attached image - and/or in http://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf).

 

So, after offsetting my A53 application, everything was just fine.

View solution in original post

2016-05-17 14_45_12-Xilinx 2016.1 stuff - Evernote.png
1 Reply
egholm
Visitor
Visitor
18,496 Views
Registered: ‎05-13-2016

Ok, I will answer myself - just for the record :)

 

The reason was that I was trying to load my A53's app into a DRAM address not available from the R5.

The lower portion of the address space is reserved for addressing the R5's TCM (tightly coupled memory) (as seen from the attached image - and/or in http://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf).

 

So, after offsetting my A53 application, everything was just fine.

View solution in original post

2016-05-17 14_45_12-Xilinx 2016.1 stuff - Evernote.png