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stefangriebel
Observer
Observer
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Registered: ‎11-09-2011

Multiple SDK JTAG UART Connections

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I am using SDK 2019.1, attempting to communicate with 2 separate FPGAs simultaneously using 2 separate JTAG cables. I was able to program them simultaneously by manually selecting the appropriate JTAG cable in SDK's FPGA programming options. Moving on to software debug, I specify the FPGA device for both projects in the Run/Debug Settings like so:

debug_settings_fpga_device.png

Now I can peek/poke registers for the 2 FPGAs fine on my Microblaze/MDM AXI bus manually using XSCT, but when I try to launch code on one FPGA, I get info echoed to both XSCT terminals, and my normally working JTAG UART interaction via the Console (TCF Debug Virtual Terminal) is completely broken on both sides. I have also issued a "jtag target -set" command in each SDK's XSCT Console trying to resolve this.

The following screen grab shows:

  • successful AXI bus reads (right XSCT)
  • successful launch of code (left XSCT)
  • mirrored Info messages (both XSCTs)
  • reported jtag targets (both XSCTs)
  • Empty TCF Debug terminal, which is normally an interactive JTAG virtual UART.

jtag_targets.png

What would be the next step in getting this to work reliably?

 

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marcb
Moderator
Moderator
747 Views
Registered: ‎05-08-2012

Hi @stefangriebel 

Can you try the following steps to debug multiple boards:

To debug on multiple development boards, a separate JTAG port can be used. First, each boards serial number will need to be found for the next command.

    

marcb_0-1607987994491.png

 

    

marcb_1-1607987994495.png

 



Below is the syntax to start two separate hw_server instances using different JTAG ports. The first does not require a port designation, and uses the default of 3121. This can be done from separate Vivado Tcl shell command prompts.

hw_server -e "set jtag-port-filter <serial_number_1>"
hw_server -s tcp::3122 -e "set jtag-port-filter <serial_number_2>"

marcb_2-1607987994502.png

 



marcb_3-1607987994506.png

 



Next, open up two separate Vitis (or Xilinx SDK) sessions for each board/application combination that will be targeted. The session using the default port (3121) does not need the Target Connections altered. However, the second session using port 3122 does. Below shows opening the Target connections.

marcb_4-1607987994510.png

 

     

marcb_5-1607987994512.png

 



Target Connections for the default port 3121

marcb_6-1607987994514.png

 




Target Connections for the additional port 3122. 

marcb_7-1607987994517.png

 



Once these have been set. Debug on each session can proceed as normal without one debug connection interfering with the other. The same steps can be used with Xilinx SDK as well.

 

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3 Replies
marcb
Moderator
Moderator
748 Views
Registered: ‎05-08-2012

Hi @stefangriebel 

Can you try the following steps to debug multiple boards:

To debug on multiple development boards, a separate JTAG port can be used. First, each boards serial number will need to be found for the next command.

    

marcb_0-1607987994491.png

 

    

marcb_1-1607987994495.png

 



Below is the syntax to start two separate hw_server instances using different JTAG ports. The first does not require a port designation, and uses the default of 3121. This can be done from separate Vivado Tcl shell command prompts.

hw_server -e "set jtag-port-filter <serial_number_1>"
hw_server -s tcp::3122 -e "set jtag-port-filter <serial_number_2>"

marcb_2-1607987994502.png

 



marcb_3-1607987994506.png

 



Next, open up two separate Vitis (or Xilinx SDK) sessions for each board/application combination that will be targeted. The session using the default port (3121) does not need the Target Connections altered. However, the second session using port 3122 does. Below shows opening the Target connections.

marcb_4-1607987994510.png

 

     

marcb_5-1607987994512.png

 



Target Connections for the default port 3121

marcb_6-1607987994514.png

 




Target Connections for the additional port 3122. 

marcb_7-1607987994517.png

 



Once these have been set. Debug on each session can proceed as normal without one debug connection interfering with the other. The same steps can be used with Xilinx SDK as well.

 

---------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------

View solution in original post

stefangriebel
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Registered: ‎11-09-2011

Thanks, worked perfectly!

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stefangriebel
Observer
Observer
533 Views
Registered: ‎11-09-2011

Hi again-

This solution was working perfectly for me on a Windows 7 machine. Now that we upgraded to Windows 10, as soon as I start the 2nd hw_server on port 3122, neither the SDK nor Vivado can access hardware from the 2nd port. Is there some additional setting (IT security maybe?) that I need to check to ensure I can communicate to the JTAG on a non-default port?

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