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Voyager
Voyager
3,546 Views
Registered: ‎05-09-2008

New SDRAM memory for custom board ...

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Hi,

 

I have new board with Spartan3A DSP and "IS42S32800D-7" SDRAM. This SDRAM is not in the database file "mpmc_memory_database.csv" of EDK. This is not a problem. I manually added the device and all works fine. 

 

Now I develop a new file "xbd" for a custom board but i have some problem with PARAMETER C_MEM_PARTNO = "CUSTOM". I have add all parameter for SDRAM in "xbd" file but after generate EDK project and generate bitstream i obtain an error.

 

In File "XBD" :

 

 

### SDRAM ### BEGIN IO_INTERFACE ATTRIBUTE IOTYPE = XIL_MEMORY_V1 ATTRIBUTE INSTANCE = SDRAM PARAMETER C_MEM_PARTNO = "CUSTOM", IO_IS = C_MEM_PARTNO PARAMETER C_MEM_TYPE = SDRAM, IO_IS = C_MEM_TYPE PARAMETER C_MEM_DATA_WIDTH = 32, IO_IS = C_MEM_DATA_WIDTH PARAMETER C_MEM_ADDR_WIDTH = 12, IO_IS = C_MEM_ADDR_WIDTH PARAMETER C_MEM_DM_WIDTH = 4, IO_IS = C_MEM_DM_WIDTH PARAMETER C_MEM_CE_WIDTH = 1, IO_IS = C_MEM_CE_WIDTH PARAMETER C_MEM_CLK_WIDTH = 1, IO_IS = C_MEM_CLK_WIDTH PARAMETER C_MEM_CS_N_WIDTH = 1, IO_IS = C_MEM_CS_N_WIDTH PARAMETER C_MPMC_CLK0_PERIOD_PS = 15625, IO_IS = C_MPMC_CLK0_PERIOD_PS PARAMETER C_MEM_PART_DATA_DEPTH = 256, IO_IS = C_MEM_PART_DATA_DEPTH PARAMETER C_MEM_PART_NUM_BANK_BITS = 2, IO_IS = C_MEM_PART_NUM_BANK_BITS PARAMETER C_MEM_PART_NUM_ROW_BITS = 12, IO_IS = C_MEM_PART_NUM_ROW_BITS PARAMETER C_MEM_PART_NUM_COL_BITS = 9, IO_IS = C_MEM_PART_NUM_COL_BITS PARAMETER C_MEM_PART_TRAS = 45000, IO_IS = C_MEM_PART_TRAS PARAMETER C_MEM_PART_TRASMAX = 100000000, IO_IS = C_MEM_PART_TRASMAX PARAMETER C_MEM_PART_TRC = 67500, IO_IS = C_MEM_PART_TRC PARAMETER C_MEM_PART_TRCD = 20000, IO_IS = C_MEM_PART_TRCD PARAMETER C_MEM_PART_TWR = 14000, IO_IS = C_MEM_PART_TWR PARAMETER C_MEM_PART_TRP = 20000, IO_IS = C_MEM_PART_TRP PARAMETER C_MEM_PART_TMRD = 2, IO_IS = C_MEM_PART_TMRD PARAMETER C_MEM_PART_TRRD = 14000, IO_IS = C_MEM_PART_TRRD PARAMETER C_MEM_PART_TRFC = 67500, IO_IS = C_MEM_PART_TRFC PARAMETER C_MEM_PART_TREFI = 64000000, IO_IS = C_MEM_PART_TREFI PARAMETER C_MEM_PART_TCCD = 1, IO_IS = C_MEM_PART_TCCD PARAMETER C_MEM_PART_TWTR = 0, IO_IS = C_MEM_PART_TWTR PARAMETER C_MEM_PART_DATA_WIDTH = 32, IO_IS = C_MEM_PART_DATA_WIDTH PARAMETER C_MEM_BANKADDR_WIDTH = 2, IO_IS = C_MEM_BANKADDR_WIDTH PARAMETER C_MEM_NUM_DIMMS = 1, IO_IS = C_MEM_NUM_DIMMS PARAMETER C_MEM_NUM_RANKS = 1, IO_IS = C_MEM_NUM_RANKS PARAMETER C_MEM_PART_CAS_A_FMAX = 143, IO_IS = C_MEM_PART_CAS_A_FMAX PARAMETER C_MEM_PART_CAS_A = 3, IO_IS = C_MEM_PART_CAS_A PARAMETER C_BASEADDR = 0x00000000, IO_IS = C_BASEADDR PARAMETER C_HIGHADDR = 0x007FFFFF, IO_IS = C_HIGHADDR PORT sdram_DQ0 = sdram_DQ0, IO_IS = sdram_data[0] PORT sdram_DQ1 = sdram_DQ1, IO_IS = sdram_data[1] PORT sdram_DQ2 = sdram_DQ2, IO_IS = sdram_data[2] PORT sdram_DQ3 = sdram_DQ3, IO_IS = sdram_data[3] PORT sdram_DQ4 = sdram_DQ4, IO_IS = sdram_data[4] PORT sdram_DQ5 = sdram_DQ5, IO_IS = sdram_data[5] PORT sdram_DQ6 = sdram_DQ6, IO_IS = sdram_data[6] PORT sdram_DQ7 = sdram_DQ7, IO_IS = sdram_data[7] PORT sdram_DQ8 = sdram_DQ8, IO_IS = sdram_data[8] PORT sdram_DQ9 = sdram_DQ9, IO_IS = sdram_data[9] PORT sdram_DQ10 = sdram_DQ10, IO_IS = sdram_data[10] PORT sdram_DQ11 = sdram_DQ11, IO_IS = sdram_data[11] PORT sdram_DQ12 = sdram_DQ12, IO_IS = sdram_data[12] PORT sdram_DQ13 = sdram_DQ13, IO_IS = sdram_data[13] PORT sdram_DQ14 = sdram_DQ14, IO_IS = sdram_data[14] PORT sdram_DQ15 = sdram_DQ15, IO_IS = sdram_data[15] PORT sdram_DQ16 = sdram_DQ16, IO_IS = sdram_data[16] PORT sdram_DQ17 = sdram_DQ17, IO_IS = sdram_data[17] PORT sdram_DQ18 = sdram_DQ18, IO_IS = sdram_data[18] PORT sdram_DQ19 = sdram_DQ19, IO_IS = sdram_data[19] PORT sdram_DQ20 = sdram_DQ20, IO_IS = sdram_data[20] PORT sdram_DQ21 = sdram_DQ21, IO_IS = sdram_data[21] PORT sdram_DQ22 = sdram_DQ22, IO_IS = sdram_data[22] PORT sdram_DQ23 = sdram_DQ23, IO_IS = sdram_data[23] PORT sdram_DQ24 = sdram_DQ24, IO_IS = sdram_data[24] PORT sdram_DQ25 = sdram_DQ25, IO_IS = sdram_data[25] PORT sdram_DQ26 = sdram_DQ26, IO_IS = sdram_data[26] PORT sdram_DQ27 = sdram_DQ27, IO_IS = sdram_data[27] PORT sdram_DQ28 = sdram_DQ28, IO_IS = sdram_data[28] PORT sdram_DQ29 = sdram_DQ29, IO_IS = sdram_data[29] PORT sdram_DQ30 = sdram_DQ30, IO_IS = sdram_data[30] PORT sdram_DQ31 = sdram_DQ31, IO_IS = sdram_data[31] PORT sdram_A0 = sdram_A0, IO_IS = sdram_address[0] PORT sdram_A1 = sdram_A1, IO_IS = sdram_address[1] PORT sdram_A2 = sdram_A2, IO_IS = sdram_address[2] PORT sdram_A3 = sdram_A3, IO_IS = sdram_address[3] PORT sdram_A4 = sdram_A4, IO_IS = sdram_address[4] PORT sdram_A5 = sdram_A5, IO_IS = sdram_address[5] PORT sdram_A6 = sdram_A6, IO_IS = sdram_address[6] PORT sdram_A7 = sdram_A7, IO_IS = sdram_address[7] PORT sdram_A8 = sdram_A8, IO_IS = sdram_address[8] PORT sdram_A9 = sdram_A9, IO_IS = sdram_address[9] PORT sdram_A10 = sdram_A10, IO_IS = sdram_address[10] PORT sdram_A11 = sdram_A11, IO_IS = sdram_address[11] PORT sdram_DM0 = sdram_DM0, IO_IS = sdram_data_mask[0] PORT sdram_DM1 = sdram_DM1, IO_IS = sdram_data_mask[1] PORT sdram_DM2 = sdram_DM2, IO_IS = sdram_data_mask[2] PORT sdram_DM3 = sdram_DM3, IO_IS = sdram_data_mask[3] PORT sdram_WEn = sdram_WEn, IO_IS = sdram_write_enable PORT sdram_CKe = sdram_CKe, IO_IS = sdram_clk_enable PORT sdram_CSn = sdram_CSn, IO_IS = sdram_chip_select PORT sdram_CASn = sdram_CASn, IO_IS = sdram_col_addr_select PORT sdram_RASn = sdram_RASn, IO_IS = sdram_row_addr_select PORT sdram_CLK = sdram_CLK, IO_IS = sdram_clk PORT sdram_BA0 = sdram_BA1, IO_IS = sdram_bankaddr[0] PORT sdram_BA1 = sdram_BA0, IO_IS = sdram_bankaddr[1] END

 

Someone has ever done ?

 

Kappa.

 

 

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4,182 Views
Registered: ‎08-21-2008

Re: New SDRAM memory for custom board ...

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Hello.

Sry for the delayed response as i did XBD for 9.1 only and never tried on 10.1. So i was doing it for 10.1 and its successful. I am using version 10.1.03. I am pasting it below for SDRAM only as you require that only.

 

*********************************************************************************************************** 

BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_MEMORY_V1
  ATTRIBUTE INSTANCE = SDRAM
  PARAMETER C_MEM_PARTNO = CUSTOM, IO_IS = C_MEM_PARTNO
  PARAMETER C_MPMC_BASEADDR   = 0x00000000, IO_IS=C_BASEADDR, SHORT_DESC=SDRAM
  PARAMETER C_MPMC_HIGHADDR   = 0x00FFFFFF, IO_IS=C_HIGHADDR
  PARAMETER C_MEM_DATA_WIDTH  = 32, IO_IS = C_MEM_DATA_WIDTH
  PARAMETER C_MEM_DM_WIDTH    = 4, IO_IS = C_MEM_DM_WIDTH
  PARAMETER C_MEM_TYPE        = SDRAM, IO_IS = C_MEM_TYPE
 
PARAMETER C_MEM_CLK_WIDTH = 1,
PARAMETER C_MEM_CE_WIDTH = 1, 
PARAMETER C_MEM_CS_N_WIDTH = 1,
PARAMETER C_MEM_NUM_RANKS = 1, 
PARAMETER C_MEM_PART_CAS_A = 3,  
PARAMETER C_MEM_PART_CAS_A_FMAX = 166,  
PARAMETER C_MEM_ADDR_WIDTH = 12,   
PARAMETER C_MEM_PART_NUM_COL_BITS = 8,
PARAMETER C_MEM_PART_NUM_ROW_BITS = 12,
PARAMETER C_MEM_BANKADDR_WIDTH = 2,
PARAMETER C_MEM_PART_TMRD = 2,
PARAMETER C_MEM_PART_TWR = 15000,
PARAMETER C_MEM_PART_TCCD = 1,
PARAMETER C_MEM_PART_TRAS = 40000,
PARAMETER C_MEM_PART_TRASMAX = 120000000,
PARAMETER C_MEM_PART_TRC = 65000,
PARAMETER C_MEM_PART_TRFC = 75000,
PARAMETER C_MEM_PART_TRCD = 20000,
PARAMETER C_MEM_PART_TRRD = 15000,
PARAMETER C_MEM_PART_TRP = 20000,
PARAMETER C_MEM_PART_TREFI = 7812500,


    # Control signals are passed through registers and are multi-point,
  # each signal connected to each of the 4 sdram SDRAM devices
  PORT A0     = sdram_addr_0_,   IO_IS = sdram_address[0]
  PORT A1     = sdram_addr_1_,   IO_IS = sdram_address[1]
  PORT A2     = sdram_addr_2_,   IO_IS = sdram_address[2]
  PORT A3     = sdram_addr_3_,   IO_IS = sdram_address[3]
  PORT A4     = sdram_addr_4_,   IO_IS = sdram_address[4]
  PORT A5     = sdram_addr_5_,   IO_IS = sdram_address[5]
  PORT A6     = sdram_addr_6_,   IO_IS = sdram_address[6]
  PORT A7     = sdram_addr_7_,   IO_IS = sdram_address[7]
  PORT A8     = sdram_addr_8_,   IO_IS = sdram_address[8]
  PORT A9     = sdram_addr_9_,   IO_IS = sdram_address[9]
  PORT A10    = sdram_addr_10_,  IO_IS = sdram_address[10]
  PORT A11    = sdram_addr_11_,  IO_IS = sdram_address[11]
  PORT A12    = sdram_addr_12_,  IO_IS = sdram_address[12]

  PORT BA0    = sdram_ba_0_,     IO_IS = sdram_bankaddr[0]
  PORT BA1    = sdram_ba_1_,     IO_IS = sdram_bankaddr[1]

  PORT CAS    = sdram_cas_n,     IO_IS = sdram_col_addr_select
  PORT CKE    = sdram_ce,        IO_IS = sdram_clk_enable
  PORT CS     = sdram_cs_n,      IO_IS = sdram_chip_select
  PORT RAS    = sdram_ras_n,     IO_IS = sdram_row_addr_select
  PORT WE     = sdram_we_n,      IO_IS = sdram_write_enable

  # Point-to-point connections for data pins from FPGA to sdram SDRAM devices
  PORT DM0  = sdram_dm_0_,    IO_IS = sdram_data_mask[0]
  PORT DM1  = sdram_dm_1_,    IO_IS = sdram_data_mask[1]
  PORT DM2  = sdram_dm_2_,    IO_IS = sdram_data_mask[2]
  PORT DM3  = sdram_dm_3_,    IO_IS = sdram_data_mask[3]

  PORT DQ0 = sdram_dq_0_,    IO_IS = sdram_data[0]
  PORT DQ1 = sdram_dq_1_,    IO_IS = sdram_data[1]
  PORT DQ2 = sdram_dq_2_,    IO_IS = sdram_data[2]
  PORT DQ3 = sdram_dq_3_,    IO_IS = sdram_data[3]
  PORT DQ4 = sdram_dq_4_,    IO_IS = sdram_data[4]
  PORT DQ5 = sdram_dq_5_,    IO_IS = sdram_data[5]
  PORT DQ6 = sdram_dq_6_,    IO_IS = sdram_data[6]
  PORT DQ7 = sdram_dq_7_,    IO_IS = sdram_data[7]
  PORT DQ8 = sdram_dq_8_,    IO_IS = sdram_data[8]
  PORT DQ9 = sdram_dq_9_,    IO_IS = sdram_data[9]
  PORT DQ10 = sdram_dq_10_,   IO_IS = sdram_data[10]
  PORT DQ11 = sdram_dq_11_,   IO_IS = sdram_data[11]
  PORT DQ12 = sdram_dq_12_,   IO_IS = sdram_data[12]
  PORT DQ13 = sdram_dq_13_,   IO_IS = sdram_data[13]
  PORT DQ14 = sdram_dq_14_,   IO_IS = sdram_data[14]
  PORT DQ15 = sdram_dq_15_,   IO_IS = sdram_data[15]
  PORT DQ16 = sdram_dq_16_,   IO_IS = sdram_data[16]
  PORT DQ17 = sdram_dq_17_,   IO_IS = sdram_data[17]
  PORT DQ18 = sdram_dq_18_,   IO_IS = sdram_data[18]
  PORT DQ19 = sdram_dq_19_,   IO_IS = sdram_data[19]
  PORT DQ20 = sdram_dq_20_,   IO_IS = sdram_data[20]
  PORT DQ21 = sdram_dq_21_,   IO_IS = sdram_data[21]
  PORT DQ22 = sdram_dq_22_,   IO_IS = sdram_data[22]
  PORT DQ23 = sdram_dq_23_,   IO_IS = sdram_data[23]
  PORT DQ24 = sdram_dq_24_,   IO_IS = sdram_data[24]
  PORT DQ25 = sdram_dq_25_,   IO_IS = sdram_data[25]
  PORT DQ26 = sdram_dq_26_,   IO_IS = sdram_data[26]
  PORT DQ27 = sdram_dq_27_,   IO_IS = sdram_data[27]
  PORT DQ28 = sdram_dq_28_,   IO_IS = sdram_data[28]
  PORT DQ29 = sdram_dq_29_,   IO_IS = sdram_data[29]
  PORT DQ30 = sdram_dq_30_,   IO_IS = sdram_data[30]
  PORT DQ31 = sdram_dq_31_,   IO_IS = sdram_data[31]

  PORT sdram_FPGA_CK    = sdram_clk,    IO_IS = sdram_clk
END

*********************************************************************************************************** 

The memory size is 16 MB in my case so you take care of that and all the parametes according to your memory device. Hope that helps.

 

Message Edited by prateek_bhatt on 06-03-2009 12:37 AM
Best of luck.
--
Unlimited in my Limits.
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2 Replies
Highlighted
4,183 Views
Registered: ‎08-21-2008

Re: New SDRAM memory for custom board ...

Jump to solution

Hello.

Sry for the delayed response as i did XBD for 9.1 only and never tried on 10.1. So i was doing it for 10.1 and its successful. I am using version 10.1.03. I am pasting it below for SDRAM only as you require that only.

 

*********************************************************************************************************** 

BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_MEMORY_V1
  ATTRIBUTE INSTANCE = SDRAM
  PARAMETER C_MEM_PARTNO = CUSTOM, IO_IS = C_MEM_PARTNO
  PARAMETER C_MPMC_BASEADDR   = 0x00000000, IO_IS=C_BASEADDR, SHORT_DESC=SDRAM
  PARAMETER C_MPMC_HIGHADDR   = 0x00FFFFFF, IO_IS=C_HIGHADDR
  PARAMETER C_MEM_DATA_WIDTH  = 32, IO_IS = C_MEM_DATA_WIDTH
  PARAMETER C_MEM_DM_WIDTH    = 4, IO_IS = C_MEM_DM_WIDTH
  PARAMETER C_MEM_TYPE        = SDRAM, IO_IS = C_MEM_TYPE
 
PARAMETER C_MEM_CLK_WIDTH = 1,
PARAMETER C_MEM_CE_WIDTH = 1, 
PARAMETER C_MEM_CS_N_WIDTH = 1,
PARAMETER C_MEM_NUM_RANKS = 1, 
PARAMETER C_MEM_PART_CAS_A = 3,  
PARAMETER C_MEM_PART_CAS_A_FMAX = 166,  
PARAMETER C_MEM_ADDR_WIDTH = 12,   
PARAMETER C_MEM_PART_NUM_COL_BITS = 8,
PARAMETER C_MEM_PART_NUM_ROW_BITS = 12,
PARAMETER C_MEM_BANKADDR_WIDTH = 2,
PARAMETER C_MEM_PART_TMRD = 2,
PARAMETER C_MEM_PART_TWR = 15000,
PARAMETER C_MEM_PART_TCCD = 1,
PARAMETER C_MEM_PART_TRAS = 40000,
PARAMETER C_MEM_PART_TRASMAX = 120000000,
PARAMETER C_MEM_PART_TRC = 65000,
PARAMETER C_MEM_PART_TRFC = 75000,
PARAMETER C_MEM_PART_TRCD = 20000,
PARAMETER C_MEM_PART_TRRD = 15000,
PARAMETER C_MEM_PART_TRP = 20000,
PARAMETER C_MEM_PART_TREFI = 7812500,


    # Control signals are passed through registers and are multi-point,
  # each signal connected to each of the 4 sdram SDRAM devices
  PORT A0     = sdram_addr_0_,   IO_IS = sdram_address[0]
  PORT A1     = sdram_addr_1_,   IO_IS = sdram_address[1]
  PORT A2     = sdram_addr_2_,   IO_IS = sdram_address[2]
  PORT A3     = sdram_addr_3_,   IO_IS = sdram_address[3]
  PORT A4     = sdram_addr_4_,   IO_IS = sdram_address[4]
  PORT A5     = sdram_addr_5_,   IO_IS = sdram_address[5]
  PORT A6     = sdram_addr_6_,   IO_IS = sdram_address[6]
  PORT A7     = sdram_addr_7_,   IO_IS = sdram_address[7]
  PORT A8     = sdram_addr_8_,   IO_IS = sdram_address[8]
  PORT A9     = sdram_addr_9_,   IO_IS = sdram_address[9]
  PORT A10    = sdram_addr_10_,  IO_IS = sdram_address[10]
  PORT A11    = sdram_addr_11_,  IO_IS = sdram_address[11]
  PORT A12    = sdram_addr_12_,  IO_IS = sdram_address[12]

  PORT BA0    = sdram_ba_0_,     IO_IS = sdram_bankaddr[0]
  PORT BA1    = sdram_ba_1_,     IO_IS = sdram_bankaddr[1]

  PORT CAS    = sdram_cas_n,     IO_IS = sdram_col_addr_select
  PORT CKE    = sdram_ce,        IO_IS = sdram_clk_enable
  PORT CS     = sdram_cs_n,      IO_IS = sdram_chip_select
  PORT RAS    = sdram_ras_n,     IO_IS = sdram_row_addr_select
  PORT WE     = sdram_we_n,      IO_IS = sdram_write_enable

  # Point-to-point connections for data pins from FPGA to sdram SDRAM devices
  PORT DM0  = sdram_dm_0_,    IO_IS = sdram_data_mask[0]
  PORT DM1  = sdram_dm_1_,    IO_IS = sdram_data_mask[1]
  PORT DM2  = sdram_dm_2_,    IO_IS = sdram_data_mask[2]
  PORT DM3  = sdram_dm_3_,    IO_IS = sdram_data_mask[3]

  PORT DQ0 = sdram_dq_0_,    IO_IS = sdram_data[0]
  PORT DQ1 = sdram_dq_1_,    IO_IS = sdram_data[1]
  PORT DQ2 = sdram_dq_2_,    IO_IS = sdram_data[2]
  PORT DQ3 = sdram_dq_3_,    IO_IS = sdram_data[3]
  PORT DQ4 = sdram_dq_4_,    IO_IS = sdram_data[4]
  PORT DQ5 = sdram_dq_5_,    IO_IS = sdram_data[5]
  PORT DQ6 = sdram_dq_6_,    IO_IS = sdram_data[6]
  PORT DQ7 = sdram_dq_7_,    IO_IS = sdram_data[7]
  PORT DQ8 = sdram_dq_8_,    IO_IS = sdram_data[8]
  PORT DQ9 = sdram_dq_9_,    IO_IS = sdram_data[9]
  PORT DQ10 = sdram_dq_10_,   IO_IS = sdram_data[10]
  PORT DQ11 = sdram_dq_11_,   IO_IS = sdram_data[11]
  PORT DQ12 = sdram_dq_12_,   IO_IS = sdram_data[12]
  PORT DQ13 = sdram_dq_13_,   IO_IS = sdram_data[13]
  PORT DQ14 = sdram_dq_14_,   IO_IS = sdram_data[14]
  PORT DQ15 = sdram_dq_15_,   IO_IS = sdram_data[15]
  PORT DQ16 = sdram_dq_16_,   IO_IS = sdram_data[16]
  PORT DQ17 = sdram_dq_17_,   IO_IS = sdram_data[17]
  PORT DQ18 = sdram_dq_18_,   IO_IS = sdram_data[18]
  PORT DQ19 = sdram_dq_19_,   IO_IS = sdram_data[19]
  PORT DQ20 = sdram_dq_20_,   IO_IS = sdram_data[20]
  PORT DQ21 = sdram_dq_21_,   IO_IS = sdram_data[21]
  PORT DQ22 = sdram_dq_22_,   IO_IS = sdram_data[22]
  PORT DQ23 = sdram_dq_23_,   IO_IS = sdram_data[23]
  PORT DQ24 = sdram_dq_24_,   IO_IS = sdram_data[24]
  PORT DQ25 = sdram_dq_25_,   IO_IS = sdram_data[25]
  PORT DQ26 = sdram_dq_26_,   IO_IS = sdram_data[26]
  PORT DQ27 = sdram_dq_27_,   IO_IS = sdram_data[27]
  PORT DQ28 = sdram_dq_28_,   IO_IS = sdram_data[28]
  PORT DQ29 = sdram_dq_29_,   IO_IS = sdram_data[29]
  PORT DQ30 = sdram_dq_30_,   IO_IS = sdram_data[30]
  PORT DQ31 = sdram_dq_31_,   IO_IS = sdram_data[31]

  PORT sdram_FPGA_CK    = sdram_clk,    IO_IS = sdram_clk
END

*********************************************************************************************************** 

The memory size is 16 MB in my case so you take care of that and all the parametes according to your memory device. Hope that helps.

 

Message Edited by prateek_bhatt on 06-03-2009 12:37 AM
Best of luck.
--
Unlimited in my Limits.
0 Kudos
Voyager
Voyager
3,509 Views
Registered: ‎05-09-2008

Re: New SDRAM memory for custom board ...

Jump to solution

Hi prateek_bhatt,

 

Thaks for your replay, helped me a lot.

 

 This is a final and working XBD for SDRAM device for EDK 10.1.3:

 

 

### SDRAM ### BEGIN IO_INTERFACE ATTRIBUTE IOTYPE = XIL_MEMORY_V1 ATTRIBUTE INSTANCE = SDRAM PARAMETER C_MEM_PARTNO = "CUSTOM", IO_IS = C_MEM_PARTNO PARAMETER C_BASEADDR = 0x00000000, IO_IS = C_BASEADDR PARAMETER C_HIGHADDR = 0x007FFFFF, IO_IS = C_HIGHADDR PARAMETER C_MEM_TYPE = SDRAM, IO_IS = C_MEM_TYPE PARAMETER C_MEM_DATA_WIDTH = 32, IO_IS = C_MEM_DATA_WIDTH PARAMETER C_MEM_ADDR_WIDTH = 12, IO_IS = C_MEM_ADDR_WIDTH PARAMETER C_MEM_DM_WIDTH = 4, IO_IS = C_MEM_DM_WIDTH PARAMETER C_MEM_CE_WIDTH = 1, IO_IS = C_MEM_CE_WIDTH PARAMETER C_MEM_CLK_WIDTH = 1, IO_IS = C_MEM_CLK_WIDTH PARAMETER C_MEM_CS_N_WIDTH = 1, IO_IS = C_MEM_CS_N_WIDTH PARAMETER C_MEM_NUM_RANKS = 1, IO_IS = C_MEM_NUM_RANKS PARAMETER C_MEM_BANKADDR_WIDTH = 2, IO_IS = C_MEM_BANKADDR_WIDTH PARAMETER C_MEM_NUM_DIMMS = 1, IO_IS = C_MEM_NUM_DIMMS PARAMETER C_MEM_PART_DATA_DEPTH = 256 PARAMETER C_MEM_PART_DATA_WIDTH = 32 PARAMETER C_MEM_PART_NUM_BANK_BITS = 2 PARAMETER C_MEM_PART_NUM_ROW_BITS = 12 PARAMETER C_MEM_PART_NUM_COL_BITS = 9 PARAMETER C_MEM_PART_TRAS = 45000 PARAMETER C_MEM_PART_TRASMAX = 100000000 PARAMETER C_MEM_PART_TRC = 67500 PARAMETER C_MEM_PART_TRCD = 20000 PARAMETER C_MEM_PART_TWR = 14000 PARAMETER C_MEM_PART_TRP = 20000 PARAMETER C_MEM_PART_TMRD = 2 PARAMETER C_MEM_PART_TRRD = 14000 PARAMETER C_MEM_PART_TRFC = 67500 PARAMETER C_MEM_PART_TREFI = 64000000 PARAMETER C_MEM_PART_TCCD = 1 PARAMETER C_MEM_PART_CAS_A_FMAX = 143 PARAMETER C_MEM_PART_CAS_A = 3 PORT sdram_DQ0 = sdram_DQ0, IO_IS = sdram_data[0] PORT sdram_DQ1 = sdram_DQ1, IO_IS = sdram_data[1] PORT sdram_DQ2 = sdram_DQ2, IO_IS = sdram_data[2] PORT sdram_DQ3 = sdram_DQ3, IO_IS = sdram_data[3] PORT sdram_DQ4 = sdram_DQ4, IO_IS = sdram_data[4] PORT sdram_DQ5 = sdram_DQ5, IO_IS = sdram_data[5] PORT sdram_DQ6 = sdram_DQ6, IO_IS = sdram_data[6] PORT sdram_DQ7 = sdram_DQ7, IO_IS = sdram_data[7] PORT sdram_DQ8 = sdram_DQ8, IO_IS = sdram_data[8] PORT sdram_DQ9 = sdram_DQ9, IO_IS = sdram_data[9] PORT sdram_DQ10 = sdram_DQ10, IO_IS = sdram_data[10] PORT sdram_DQ11 = sdram_DQ11, IO_IS = sdram_data[11] PORT sdram_DQ12 = sdram_DQ12, IO_IS = sdram_data[12] PORT sdram_DQ13 = sdram_DQ13, IO_IS = sdram_data[13] PORT sdram_DQ14 = sdram_DQ14, IO_IS = sdram_data[14] PORT sdram_DQ15 = sdram_DQ15, IO_IS = sdram_data[15] PORT sdram_DQ16 = sdram_DQ16, IO_IS = sdram_data[16] PORT sdram_DQ17 = sdram_DQ17, IO_IS = sdram_data[17] PORT sdram_DQ18 = sdram_DQ18, IO_IS = sdram_data[18] PORT sdram_DQ19 = sdram_DQ19, IO_IS = sdram_data[19] PORT sdram_DQ20 = sdram_DQ20, IO_IS = sdram_data[20] PORT sdram_DQ21 = sdram_DQ21, IO_IS = sdram_data[21] PORT sdram_DQ22 = sdram_DQ22, IO_IS = sdram_data[22] PORT sdram_DQ23 = sdram_DQ23, IO_IS = sdram_data[23] PORT sdram_DQ24 = sdram_DQ24, IO_IS = sdram_data[24] PORT sdram_DQ25 = sdram_DQ25, IO_IS = sdram_data[25] PORT sdram_DQ26 = sdram_DQ26, IO_IS = sdram_data[26] PORT sdram_DQ27 = sdram_DQ27, IO_IS = sdram_data[27] PORT sdram_DQ28 = sdram_DQ28, IO_IS = sdram_data[28] PORT sdram_DQ29 = sdram_DQ29, IO_IS = sdram_data[29] PORT sdram_DQ30 = sdram_DQ30, IO_IS = sdram_data[30] PORT sdram_DQ31 = sdram_DQ31, IO_IS = sdram_data[31] PORT sdram_A0 = sdram_A0, IO_IS = sdram_address[0] PORT sdram_A1 = sdram_A1, IO_IS = sdram_address[1] PORT sdram_A2 = sdram_A2, IO_IS = sdram_address[2] PORT sdram_A3 = sdram_A3, IO_IS = sdram_address[3] PORT sdram_A4 = sdram_A4, IO_IS = sdram_address[4] PORT sdram_A5 = sdram_A5, IO_IS = sdram_address[5] PORT sdram_A6 = sdram_A6, IO_IS = sdram_address[6] PORT sdram_A7 = sdram_A7, IO_IS = sdram_address[7] PORT sdram_A8 = sdram_A8, IO_IS = sdram_address[8] PORT sdram_A9 = sdram_A9, IO_IS = sdram_address[9] PORT sdram_A10 = sdram_A10, IO_IS = sdram_address[10] PORT sdram_A11 = sdram_A11, IO_IS = sdram_address[11] PORT sdram_DM0 = sdram_DM0, IO_IS = sdram_data_mask[0] PORT sdram_DM1 = sdram_DM1, IO_IS = sdram_data_mask[1] PORT sdram_DM2 = sdram_DM2, IO_IS = sdram_data_mask[2] PORT sdram_DM3 = sdram_DM3, IO_IS = sdram_data_mask[3] PORT sdram_WEn = sdram_WEn, IO_IS = sdram_write_enable PORT sdram_CKe = sdram_CKe, IO_IS = sdram_clk_enable PORT sdram_CSn = sdram_CSn, IO_IS = sdram_chip_select PORT sdram_CASn = sdram_CASn, IO_IS = sdram_col_addr_select PORT sdram_RASn = sdram_RASn, IO_IS = sdram_row_addr_select PORT sdram_CLK = sdram_CLK, IO_IS = sdram_clk PORT sdram_BA0 = sdram_BA0, IO_IS = sdram_bankaddr[0] PORT sdram_BA1 = sdram_BA1, IO_IS = sdram_bankaddr[1] END

 

 I have noticed that the parameters with suffix "C_MEM_PART..." reported for the component not need "... , IO_IS = C_MEM_PART...". On the manual I have not found anything about it.

 

Thank you, now everything works fine.

 

Kappa.

 

 

 

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