UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer maciek11
Observer
1,539 Views
Registered: ‎07-16-2011

PCIe project XPS 13.2 ML605

Hi,

I have implemeted the exemplary project: http://www.xilinx.com/support/answers/43371.htm.

It works fine but each time I try to change something in the project I get the following errors during implementation:

 

-------------------------------------------------------------

Timing constraint: TS_CLK_125 = PERIOD TIMEGRP "CLK_125" TS_SYSCLK / 0.8 HIGH  
50% PRIORITY 1;
 
 1796440 paths analyzed, 42632 endpoints analyzed, 1281 failing endpoints
 1281 timing errors detected. (1281 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   9.345ns.
--------------------------------------------------------------------------------
Slack:                  -1.345ns (requirement - (data path - clock path skew + uncertainty))
  Source:               axi_pcie_0/axi_pcie_0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/v6_pcie_v2_3_ep_inst/pcie_2_0_i/pcie_block_i (CPU)
  Destination:          axi_pcie_0/axi_pcie_0/comp_axi_pcie_mm_s/comp_slave_bridge/comp_slave_read_cpl_tlp/tag_active<7>_2_8 (FF)
  Requirement:          8.000ns
  Data Path Delay:      9.323ns (Levels of Logic = 8)
  Clock Path Skew:      0.049ns (1.683 - 1.634)
  Source Clock:         axi_aclk_out rising at 0.000ns
  Destination Clock:    axi_aclk_out rising at 8.000ns
  Clock Uncertainty:    0.071ns
 
  Clock Uncertainty:          0.071ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.123ns
    Phase Error (PE):           0.000ns

 

-----------------------------------------------------------------------------------------------------------

Has anyone managed to successfully modify the project ?

 

I have attached both mhs and twr files.

I have been struggling with it for a while and appreciate any help!

 

Thanks,

Maciek

0 Kudos