04-21-2009 02:58 AM
Hello every one.
I am trying to build a custum FIFO periphial in PowerPC system (ML403 board). and I want to read from fifo even if It is not Empty.
then i 'm trying to make powerPC processor to wait -in case of read from fifo- until the fifo is filled with any arbitrary data. Doing this by controlling the RdAck with FIFO Empty signal. as shown in the following VHDL code.
IP2Bus_RdAck <= Bus2IP_RdCE(0) and Empty;
But there is no effect in reading and the processor read a non-valid data.
and if i write the code as below:
IP2Bus_RdAck <= Empty;
the system is hung up, and codes before the FIFO read command doesn't be performed.
How can i solve this problem, because the FIFO will filled with another system, and there is no communication between those systems.
Also, i want to transfer the CLK between both systems because i 'm using asyn FIFO.
Thus i'm trying to transfer the CLK singal using a general IO pins, is this will case any problem? becaues i have this warning message
A clock IOB clock component is not placed at an optimal
clock IOB site. The clock IOB component <fifo_ip_0_WrCLK_pin> is placed at
site <Y18>. The clock IO site can use the fast path between the IO and the
Clock buffer/GCLK if the IOB is placed in the master Clock IOB Site. This is
normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on
COMP.PIN <fifo_ip_0_WrCLK_pin.PAD> allowing your design to continue. This
constraint disables all clock placer rules related to the specified COMP.PIN.
The use of this override is highly discouraged as it may lead to very poor
timing results. It is recommended that this error condition be corrected in
and this warning will be error message if i don't write this user constrain line
NET "fifo_ip_0_WrCLK_pin" CLOCK_DEDICATED_ROUTE = FALSE;
09-22-2009 05:17 AM
yes, it will not work.
look in documentation.... ack should come on every single read, without ack, microblaze hangs, because he wait for ack.
Fifo over plb can you do in this way:
fifo counter value at register
first you read the fifo counter value,
and than you read out fifo for fifo counter value in a loop
at the end of the loop, you read fifo counter value again,
if this is zero you can finish.
09-25-2009 09:03 AM
Previous answer is correct, you need to read the documentation on the PLB slave and study the timing diagrams at the end.
However, to summarise:
The ACK must only be a single clock cycle in duration. Normally you just wrap the CeRd or CeWr back to the respective ACK to do this. This only works if your peripheral can take data or respond immediately (i.e. single clock cycle execution).
If it cannot then you have to delay sending the ACK. This will suspend the cycle but keep the inputs active. The normal way to do this is to edge detect the CeRd or CeWr to indicate the start of a cycle to your peripheral. The peripheral must respond with an ACK within 128 clock periods otherwise the PLB will timeout. It it cannot then I would suggest sending the ACK anyway but with the PLB error flag set. (Not quite sure how the PLB master handles this, but it should work).
Hope this helps.
09-25-2009 03:43 PM
I really appricaite your ideas. But the problem still exist because I can't guarantee the limit of the 128 clock periods in peripherial delays.
But I solved this problem by repalying the data with a predefined dummy word. to indicated PPC the non-validity of this read operation. I think that this is a good solution. because my system speed is the first periority in my design. And reading the peripherial time-out status or the FIFO word count register value consume time longer than my suggestion because it needs to get another read cycle, in addition to the first read cycle, with the IO peripherial but the operation of comparsion with the dummy word is done within the processor's cycles without any aditionial read IO cycle.
Thank you in advance