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Visitor chrisab508
Visitor
8,316 Views
Registered: ‎11-11-2015

PLB to AXI Endian Byte Swap

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Hello Everyone,

I have an EDK project with an AXI processor, an AXI to PLB bridge, an XPS_TFT controller, MPMC, and an NPI interface to write my data to the video memory on the DDR.  I had an issue with my colors not displaying correctly, after looking into this issue a bit more (thanks to the Xilinx forums) I discovered the endian swap between AXI and PLB.  A few questions:

 

1. I performed the swap manually in my VHDL for both my write addresses (32 bits) and my write data (32) bits and this did NOT work.  Instead, I performed the swap on just the write data (leaving the addresses alone) and this did work.  Why is this happening? I would expect to have to perform the swap on both sets

 

2. Looking at the axi to plb bridge, there is an "enable byte swap" check box.  I had this unchecked originally (thus the need for my manual VHDL swapping).  I did an experiment, where I disabled my manual VHDL swapping, enabled the byte swap in the bridge, re-generated my netlist, rebuilt everything and gave it a try and....my colors were still wrong!  What is this check-box actually doing?

 

Any help with this would be great!

 

Thank you,

 

Chris

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Instructor
Instructor
15,831 Views
Registered: ‎08-14-2007

Re: PLB to AXI Endian Byte Swap

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I'm not sure what the check box does, but the address should never be byte swapped.  The only reason you need to byte swap data when changing from big to little Endian is the fact that data can be written as bytes as well as words.  Addess on the other hand is only used as a complete bus - it makes no sense to write a byte out of the address.

 

In any case, the sort of brain-dead byte-swapping implemented in the PLB to AXI bridge generally requires fixing in your HDL.  That's because it really only makes sense to byte-swap data that has been written as bytes.  Any data that gets written as short or long integers would require different swapping or no swapping depeneding on the bus size vs. data size.

-- Gabor
3 Replies
Instructor
Instructor
15,832 Views
Registered: ‎08-14-2007

Re: PLB to AXI Endian Byte Swap

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I'm not sure what the check box does, but the address should never be byte swapped.  The only reason you need to byte swap data when changing from big to little Endian is the fact that data can be written as bytes as well as words.  Addess on the other hand is only used as a complete bus - it makes no sense to write a byte out of the address.

 

In any case, the sort of brain-dead byte-swapping implemented in the PLB to AXI bridge generally requires fixing in your HDL.  That's because it really only makes sense to byte-swap data that has been written as bytes.  Any data that gets written as short or long integers would require different swapping or no swapping depeneding on the bus size vs. data size.

-- Gabor
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Xilinx Employee
Xilinx Employee
8,197 Views
Registered: ‎08-06-2007

Re: PLB to AXI Endian Byte Swap

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Hi,

 

Endianness is always a interesting topic.

It is never a problem if the only source of reading and writing is only from the processor but as soon as you have another source or are using data-formats that are endianness specific, you can run in to issues.

 

There is a problem with hardware endian conversion that it can't be 100% correct since endianness is software dependent.

Most processors will do a 32-bit read independent if it just needs one byte or one half-word or one 32-bit word.

If your software only handles 32-bit data and your processor is 32-bit, reading and writing 32-bit data is not affected by the endianness at all. It is the same for both little and big-endian format.

If your software are using 8-bit data, you will need to do an endianness conversion either in hardware (as you have done) or in software.

However if your software are also using 16-bit data, you need another endianness conversion and this is where the problems occurs. 

The hardware endianness conversions can't know if the software will be consider the 32-bit data read as 32-bit, 16-bit or 8-bit since the processor will just issue a 32-bit read instruction.

 

Göran

 

 

 

 

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Instructor
Instructor
8,184 Views
Registered: ‎08-14-2007

Re: PLB to AXI Endian Byte Swap

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Years ago I worked at a company that made bus-to-bus link hardware.  These were used mainly in 32-bit minicomputers and had to convert data from one bus format to another, for example VME bus to Unibus.  Because often one processor was big endian and the other little endian, the link allowed access through three different address windows, one each for unswapped, 16-bit swapped, and byte-swapped.  That allowed the software to choose the right window for the data type in use while allowing the hardware to do the actual swapping.  There's no reason you couldn't make a PLB to AXI bridge with multiple address windows, except that you would need to have the address space to spare.  In the days when we made those bus links, computers typically had much less memory installed than the address space supported.

-- Gabor
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