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Explorer
Explorer
4,481 Views
Registered: ‎01-25-2008

PPC405 DMA and DCache -> How to create a shadow memory?

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Hi,

Im using EDK10.1, PPC405 in a XC4VFX20, MPMC4.03.

 

My system has 128MB DDR (from 0x00000000 to 0x07FFFFFFF).  In this DDR I have several video buffers.

I have a 2D graphics controller which performs DMA transactions to and from the DDR via a PLB port on the MPMC.  The 2D graphics controller is used for basic operations such as line drawing, filling, memory copy, etc.  It is blindingly fast compared with issuing software instructions.

 

I now wish to enable caches in my system to boost the performance even futher. I call:

XCache_EnableICache(0x800000000);

XCache_EnableDCache(0x800000000);

 

The system keeps working, but the graphics are not good.  It is clearly a problem with DMA and the Cache Coherency.

I tried to switch the caches on and off during DMA transfer from the 2D controller and the problem went away, but there was  a massive performance hit calling cache enable so often.

 

So I want to create a shadow memory (somehow)!!??

 

I would like to put this memory in the range of 0x08000000 to 0x0FFFFFFF.

 

Can anyone sugest how I would do this?  Could I create a PLB to PLB bridge and somehow do address mapping?

Or is there anyway I can set a cache bypass flag on the video buffer memory region?

 

Thanks

Lachlan.

 

 

Lachlan Grogan
CEO, SIL3 Pty Ltd
Melbourne, Australia
http://sil3.com.au
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1 Solution

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Xilinx Employee
Xilinx Employee
5,821 Views
Registered: ‎07-30-2007

Re: PPC405 DMA and DCache -> How to create a shadow memory?

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You should be able to create an additional PLB PIM on the MPMC with a different address range.  No need for a bridge.

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4 Replies
Xilinx Employee
Xilinx Employee
5,822 Views
Registered: ‎07-30-2007

Re: PPC405 DMA and DCache -> How to create a shadow memory?

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You should be able to create an additional PLB PIM on the MPMC with a different address range.  No need for a bridge.

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Explorer
Explorer
4,454 Views
Registered: ‎01-25-2008

Re: PPC405 DMA and DCache -> How to create a shadow memory?

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Thanks Dylan,

 

You have pointed me in the right spot.

 

MPMC 4.03a Datasheet page 37:

 

 

Base/High/Offset Parameters

If you want to implement a shadow or aliased memory you need to double the amount of addressable memory. This can be done by increasing the C_<PIM_Type>_HIGHADDR by an amount that will double the address range.

 

Cheers

Lachlan.

 

Lachlan Grogan
CEO, SIL3 Pty Ltd
Melbourne, Australia
http://sil3.com.au
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Observer abhisek.bakshi
Observer
4,354 Views
Registered: ‎08-09-2010

DMA error

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Hi,

     I was trying to transfer data through DMA core. To enable interrupt I used XDmaCentral_InterruptEnableSet() function. But when using this function an error is generated. It is shown that  "region ilmb_cntlr_dlmb_cntlr is full". Could anyone please tell the meaning of the error and how it can be removed.

thanks in advance.

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Explorer
Explorer
4,345 Views
Registered: ‎01-25-2008

Re: DMA error

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Hi,

 

I think the "region full" error is more related to compile time issues.. 

 

You should revise your linker script, and if necessary enlarge the size of the RAM you are using, or reduce the size of the program code.  By calling the XDMACentral..() funtion, you are actually using the library function, which will take more space..

 

Lachlan.

Lachlan Grogan
CEO, SIL3 Pty Ltd
Melbourne, Australia
http://sil3.com.au
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