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Explorer
Explorer
6,508 Views
Registered: ‎08-18-2011

Packaging AXI 4 Design

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How is C S00 AXI BASEADDR communicated to the design from the gui? - the other items have generics

 

my_ip_block.PNG

 

my_ip_hdl.PNG

 

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Explorer
Explorer
10,610 Views
Registered: ‎08-18-2011

Re: Packaging AXI 4 Design

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Update:

 

Address translation works by hand in hdl.

 

 

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Scholar muravin
Scholar
6,495 Views
Registered: ‎11-21-2013

Re: Packaging AXI 4 Design

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Hello,

 

If you are coming from XPS experience, the addressing is entirely offloaded onto the AXI Interconnect, not the IP, the way it was in the XPS.

 

That is, the address decoding logic is no longer part of the IP, but it is part of the AXI Interconnect.

 

Regards

Vlad

Vladislav Muravin
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Explorer
Explorer
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Registered: ‎08-18-2011

Re: Packaging AXI 4 Design

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So if i'm instantiating the IP in hdl, how does it know what its address is?

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Scholar muravin
Scholar
6,488 Views
Registered: ‎11-21-2013

Re: Packaging AXI 4 Design

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If you are only instantiating the IP in HDL, then the IP does not know and does not have to know its address. I know it sounds weird, but this is the new reality. You *can* still maintain the address on your IP but it has to be in sync with the external address map definition in VIVADO.

 

Regards

Vladislav Muravin
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Explorer
Explorer
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Registered: ‎08-18-2011

Re: Packaging AXI 4 Design

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ok - so I do all the address translation myself?

 

I have an axi interconnect in a block diagram that exposes AXI master ports to the fabric - it seems like the address translation should happen there.

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Explorer
Explorer
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Registered: ‎08-18-2011

Re: Packaging AXI 4 Design

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Update:

 

Address translation works by hand in hdl.