11-06-2014 07:22 AM
If you are coming from XPS experience, the addressing is entirely offloaded onto the AXI Interconnect, not the IP, the way it was in the XPS.
That is, the address decoding logic is no longer part of the IP, but it is part of the AXI Interconnect.
11-06-2014 07:41 AM
If you are only instantiating the IP in HDL, then the IP does not know and does not have to know its address. I know it sounds weird, but this is the new reality. You *can* still maintain the address on your IP but it has to be in sync with the external address map definition in VIVADO.
11-06-2014 09:16 AM
ok - so I do all the address translation myself?
I have an axi interconnect in a block diagram that exposes AXI master ports to the fabric - it seems like the address translation should happen there.