UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Participant jmnorse
Participant
4,107 Views
Registered: ‎04-07-2009

Partial Reconfiguration of Embedded Design

Jump to solution

Hi,

Has anyone gotten an EDK design to work when it's dynamically loaded into a reconfigurable partition? I'm seeing some very strange behavior...

 

My setup:

Initial bitstream is a static EDK design, EDK1, and an empty reconfigurable region, RM1.

  EDK1 controls the ICAP and is responsible for retrieving RM2 from flash and loading it.

RM2 contains a second EDK design, EDK2, that is completely separate from EDK1.

 

EDK1 controls the reset into EDK2 as well as all the decoupling logic that is used during dynamic reconfiguration.

 

The outputs from the tools are:

  initial bitstream (EDK1 + RM1)

  final bitstream (EDK1 + RM2/EDK2)

  partial bitstream (RM2/EDK2).

 

 

My problem:

If I configure with the final bitstream, I can connect to EDK2 using the MDM module and verify that it runs its SW exectuable correctly.

If I configure with the initial bitstream, have EDK1 enable the decoupling logic, use iMPACT to dynamically reconfigure the FPGA with RM2, have EDK1 cycle RM2 reset and disable the decoupling logic, I see serious problems.  I use XMD to do low level queries with the microblaze.  If I do mw and mrd over the LMB to processor memory (BRAMS), I see stuck bits and inverted bits.  IE, if I write 0xDEADBEEF, I consistantly read back 0xDEAE7EEF.  If I write 0x00000000, I read back 0x0000C000.  Also, mw and mrd over PLB show that the PLB is stuck at all 0's.

 

I'm unable to account for why there would be differences in how the bus looks. Does anyone have any idea why this might be happening?

 

Thanks,

Justin

0 Kudos
1 Solution

Accepted Solutions
Participant jmnorse
Participant
5,260 Views
Registered: ‎04-07-2009

Re: Partial Reconfiguration of Embedded Design

Jump to solution

I think I have the problem solved. I was working with the PR guys through webcase.

 

1) All clock used by logic in the reconfigurable partition (RP) should be gated during reconfiguration. This can be controlled using the BUFGCE primitives. Gating the clock keeps things like the SRLs from destroying their init state before the RP is ready to run.

 

2) I needed to upgrade to planahead/edk 13.2. I was using 12.2 due to licensing issues with my PR license. There must have been fixed in planahead that were needed.

 

Justin

0 Kudos
4 Replies
Participant jmnorse
Participant
4,091 Views
Registered: ‎04-07-2009

Re: Partial Reconfiguration of Embedded Design

Jump to solution

Update: It looks like the LMB is actually modifying the data in a consitant manner. It consistantly adds 0x0000C000 to any data. Hence, 0x00000000 becomes 0x0000C000, 0xFFFF40000 becomes 0x00000000, and so forth.

 

Justin

0 Kudos
Highlighted
Explorer
Explorer
4,087 Views
Registered: ‎08-12-2007

Re: Partial Reconfiguration of Embedded Design

Jump to solution
It looks strange and hard to debug.

Check the timing of your design, especially the timing paths including proxy logic.

XMD uses BSCAN. Can you test your design without involving BSCAN? For example, let the EDK2 run hello world as soon as it is reconfigured and reset?

You can also try to run the implementation with another cost table. When all timing requirements are met, test it again to check whether all the behaviors are the same.
0 Kudos
Participant jmnorse
Participant
4,075 Views
Registered: ‎04-07-2009

Re: Partial Reconfiguration of Embedded Design

Jump to solution

Ricky,

I believe the timing should be ok. I say this since when I configure with the final bitstream, I have no issues. Additionally, after many many tries in previous weeks, I've gotten all my timing issues solved and now consistently get timing scores of 0 for all builds.

 

My BSCAN is implemented in the static region. I had to make the MDM local to my EDK2 project and manually move the BSCAN since BSCAN primitives are not allowed in reconfigurable partitions (RPs). Again, when I configure with the full bitstream, the debug interaction is good. If I do the partial reconfiguration starting from my initial bitstream, I get no UART output. I tried this with and without the MDM (and hence BSCAN) in the design. Given what I observe with the MDM in the design, I believe that in both cases, the processor memory and the uBlaze are thoroughly messed up.

 

I've found at least one problem and I'm going up the webcase chain to get Xilinx's opinion. The EDK and CoreGen tools use SRLs like crazy. In my opinion, the SRL is a weak design element since it contains a register and NO reset input. Everyone's opinion is why bother with a reset when the GSR line can be used to force an initialization value. Well, I personally always use a reset and PR is a vindicating example of why reset should always be used. PR does not assert the GSR line and any register lacking a non-GSR reset will come out of PR with whatever random value happened to be there before the slice was reconfigured.

 

I suspect that EDK design can't be used in a reconfigurable partition....  scary :(

 

Justin

 

0 Kudos
Participant jmnorse
Participant
5,261 Views
Registered: ‎04-07-2009

Re: Partial Reconfiguration of Embedded Design

Jump to solution

I think I have the problem solved. I was working with the PR guys through webcase.

 

1) All clock used by logic in the reconfigurable partition (RP) should be gated during reconfiguration. This can be controlled using the BUFGCE primitives. Gating the clock keeps things like the SRLs from destroying their init state before the RP is ready to run.

 

2) I needed to upgrade to planahead/edk 13.2. I was using 12.2 due to licensing issues with my PR license. There must have been fixed in planahead that were needed.

 

Justin

0 Kudos