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Registered: ‎03-01-2010

Peripheral Import/EDK Build Problems: ERROR:NgdBuild:604 - logical block ... could not be resolved

Dear Xilinx minded people:


I have an EDK design in xps 12.4 .  I created a fifo in ISE Project Navigator 12.4 using CORE Generator called "myfifo".  I then imported "myfifo" into my EDK design using the peripheral import feature of xps (I pointed it to the VHLD wrapper file that ISE generated).  I instantiated it in xps, called it "data0_fifo" and connected it.  Everthing seems to be fine except I get the following error when I try to build:


ERROR:NgdBuild:604 - logical block 'data0_fifo/data0_fifo' with type 'myfifo'
   could not be resolved. A pin name misspelling can cause this, a missing edif
   or ngc file, case mismatch between the block name and the edif or ngc file
   name, or the misspelling of a type name. Symbol 'myfifo' is not supported in
   target 'virtex5'.



I am not sure if this has anything to do with my problem, but the only thing that I can think of is that xps needs more that just the wrapper file that I imported for "myfifo".  I noticed that myfifo.vhd, the file that I imported into xps, has the line in it:


for all : wrapped_myfifo use entity XilinxCoreLib.fifo_generator_v7_2(behavioral)


Do I have to somehow point xps to XilinxCoreLib.fifo_generator_v7_2(behavioral) also?


Is there anything else that I have to import for this to work?  Or should xps be able to deal with it?


Can anyone help me?  Thanks.


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Xilinx Employee
Xilinx Employee
Registered: ‎08-02-2007



Try to follow this procedure as mentioned in this AR



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