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Explorer
Explorer
2,382 Views
Registered: ‎12-02-2012

Pin assignments for modules

I have a (what I hope is) fairly simple EDK project that has a DDR3, microblaze, ethernetlite, uart, interconnects, interrupt controller, and the attendent clock generator and lmb modules. Long term goal, this is intended to allow me to replace the old edk project that comes with the OpenSPARC package so I can run this on the Virtex7 base board. Short term, I just want this thing to generate a bitstream with the current components. The attempt fails because of the following error:

 

ERROR:Bitgen:342 - This design contains pins which have locations (LOC) that are
   not user-assigned or I/O Standards (IOSTANDARD) that are not user-assigned.
   This may cause I/O contention or incompatibility with the board power or
   connectivity affecting performance, signal integrity or in extreme cases
   cause damage to the device or the components to which it is connected.  To
   prevent this error, it is highly suggested to specify all pin locations and
   I/O standards to avoid potential contention or conflicts and allow proper
   bitstream creation.  To demote this error to a warning and allow bitstream
   creation with unspecified I/O location or standards, you may apply the
   following bitgen switch: -g UnconstrainedPins:Allow

 

And the ports it is complaining about are the following:

 

This message applies to the following I/O ports:
   RESET
   Generic_EMAC_TX_ER
   PHY_rx_clk
   PHY_rx_data<2>
   RS232_Uart_1_sin
   PHY_crs
   PHY_rx_data<0>
   PHY_rx_data<1>
   PHY_rst_n
   PHY_MDC
   PHY_rx_data<3>
   PHY_tx_data<1>
   PHY_tx_data<3>
   Generic_EMAC_TX_EN
   PHY_rx_er
   PHY_tx_clk
   PHY_MDIO
   PHY_dv
   PHY_tx_data<0>
   PHY_tx_data<2>
   RS232_Uart_1_sout
   CLK_P
   CLK_N

 

So ironically, not the memory module, which I thought was going to be the biggest pain (though that might just be because it error'ed out before it got there). Right now I'm looking for pointers as to how to proceed. The warning seems to indicate I need to manually assign pin locations but I haven't really found any documentation discussion how to do that. My impression, perhaps a mistaken one, was that these pin assignments would be generated by the EDK.

 

Looking back up, I see lots of warnings like this:

 

WARNING:LIT:701 - PAD symbol "PHY_tx_clk" has an undefined IOSTANDARD.
WARNING:LIT:702 - PAD symbol "PHY_tx_clk" is not constrained (LOC) to a specific

 

Which I presume is part of the problem, but I am unsure how I'm supposed to solve it or what documentation I'm supposed to look at to learn how to assign these pins or get EDK to assign them for me.

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Mentor hgleamon1
Mentor
2,379 Views
Registered: ‎11-14-2011

Re: Pin assignments for modules

Do you have a .UCF? If not, you need one. If you don't know what that is, look up the Xilinx Constraints Guide.

 

Regards,

 

Howard

 

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"That which we must learn to do, we learn by doing." - Aristotle
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