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Participant mportola
Participant
3,066 Views
Registered: ‎02-10-2012

PlanAhead error when implementing DPRAM

Hello,

 

I am implementing a Zynq peripherals using a bunch of double-port memories, implemented using the "BRAM_TDP_MACRO". Everyting works fine until I try to set an initialization file in the generic map, like this:

 

BRAM_TDP_MACRO_inst : BRAM_TDP_MACRO
generic map (
BRAM_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb"
DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
DOA_REG => 0, -- Optional port A output register (0 or 1)
DOB_REG => 0, -- Optional port B output register (0 or 1)
INIT_A => X"000000000", -- Initial values on A output port
INIT_B => X"000000000", -- Initial values on B output port
-- INIT_FILE => init_file,
INIT_FILE => "RX_DATA_AC1_I.mif",
 READ_WIDTH_A => 16, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")

... etc ... 

 

Then at the Implementation step PlanAhead gives me this error: 

 

ERROR::11 - Unexpected symbol '.', 'COMPONENT_INFO 'c' instance name or '*' wild' expected.
-mf n module_2_stub h asynch_iq_gw_0/USER_LOGIC_I/gps_int/from_RRH_S7.from_RRH_rx_data_ac1_i/ten_bit_address_bram.BRAM_TDP_MACRO_inst/ramb_bl.ramb18_dp_bl.ram18_bl module_2_i/asynch_iq_gw_0 c module_2_i_asynch_iq_gw_0_asynch_iq_gw_0_USER_LOGIC_I_gps_int_from_RRH_S7.from_RRH_rx_data_ac1_i_ten_bit_address_bram.BRAM_TDP_MACRO_inst_ramb_bl.ramb18_dp_bl.ram18_bl_range module_2_i/asynch_iq_gw_0/asynch_iq_gw_0/USER_LOGIC_I/gps_int/from_RRH_S7.from_RRH_rx_data_ac1_i/ten_bit_address_bram.BRAM_TDP_MACRO_inst/ramb_bl.ramb18_dp_bl.ram18_bl RAMB18 [17:0] [0:1023] << RX_DATA_AC1_I.mif a module_2_i_asynch_iq_gw_0_asynch_iq_gw_0_USER_LOGIC_I_gps_int_from_RRH_S7.from_RRH_rx_data_ac1_i_ten_bit_address_bram.BRAM_TDP_MACRO_inst_ramb_bl.ramb18_dp_bl.ram18_bl module_2_i/asynch_iq_gw_0/asynch_iq_gw_0/USER_LOGIC_I/gps_int/from_RRH_S7.from_RRH_rx_data_ac1_i/ten_bit_address_bram.BRAM_TDP_MACRO_inst/ramb_bl.ramb18_dp_bl.ram18_bl 0 18 module_2_i_asynch_iq_gw_0_asynch_iq_gw_0_USER_LOGIC_I_gps_int_from_RRH_S7.from_RRH_rx_data_ac1_i_ten_bit_address_bram.BRAM_TDP_MACRO_inst_ramb_bl.ramb18_dp_bl.ram18_bl_range

 

What does this mean? It looks like something in the expanded name .... 

 

I also add the log for better readability. 

 

Thanks,

 

Michele

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2 Replies
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Contributor
Contributor
2,975 Views
Registered: ‎10-06-2010

Re: PlanAhead error when implementing DPRAM

I have seen the same problem.

Were you able to solve the problem ?

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Participant mportola
Participant
2,967 Views
Registered: ‎02-10-2012

Re: PlanAhead error when implementing DPRAM

Xilinx told me the issue is in the pipe to be solved in a future release, but I don't knwo which. 

For the moment I made a workaround using initialization modules loading the DPRAM at startup. I made a through validation in simulation, and everything went fine once implemented.

 

Michele

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