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lucius1985
Observer
Observer
7,850 Views
Registered: ‎03-03-2010

Port connected to GND - Error Xst 2033

Hi!

I am trying to connect my IP to a DDR2 RAM controller that I have created with CoreGenerator. 

The problem is as follows: after creating the controller with MIG tool, I have make an ISE project where I have included my logic and my memory controller connected them.After that, I have imported that IP to my EDK project and connected it to the PLB bus, and then try to generate bitstream. But in that process, it has appeared the following message in the console:

 

ERROR:Xst:2033 - Port I of Input buffer mp2ram_0/USER_LOGIC_I/RAM_Interface/u_ddr2_infrastructure/DIFF_ENDED_CLKS_INST.SYS_CLK_INST is connected to GND
ERROR:Xst:2033 - Port IB of Input buffer mp2ram_0/USER_LOGIC_I/RAM_Interface/u_ddr2_infrastructure/DIFF_ENDED_CLKS_INST.SYS_CLK_INST is connected to GND
ERROR:Xst:2033 - Port I of Input buffer mp2ram_0/USER_LOGIC_I/RAM_Interface/u_ddr2_infrastructure/DIFF_ENDED_CLKS_INST.IDLY_CLK_INST is connected to GND
ERROR:Xst:2033 - Port IB of Input buffer mp2ram_0/USER_LOGIC_I/RAM_Interface/u_ddr2_infrastructure/DIFF_ENDED_CLKS_INST.IDLY_CLK_INST is connected to GND

 

Does anyone know why it happens? How can I solve it? Thank you very much.

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7 Replies
htsvn
Xilinx Employee
Xilinx Employee
7,846 Views
Registered: ‎08-02-2007

Hi,

 

Try to port the MIG signal out on top level.

 

Thnx

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lucius1985
Observer
Observer
7,843 Views
Registered: ‎03-03-2010

Thanks for your response!

Which MIG signals, the ones which are grounded? I already have done it (or at least, I think so). In the file ddr2_infraestructure there is this code

 

DIFF_ENDED_CLKS_INST : if(CLK_TYPE = "DIFFERENTIAL") generate
  begin
    --**************************************************************************
    -- Differential input clock input buffers
    --**************************************************************************

    SYS_CLK_INST : IBUFGDS_LVPECL_25
      port map (
        I  => sys_clk_p,
        IB => sys_clk_n,

        O  => sys_clk_ibufg
        );

    IDLY_CLK_INST : IBUFGDS_LVPECL_25
      port map (
        I  => clk200_p,
        IB => clk200_n
,
        O  => clk200_ibufg
        );

  end generate;

 

where you can see with red bolt font the signals grounded. 

I have routed that signals to my top level file, which is:

 

port
  (
    -- ADD USER PORTS BELOW THIS LINE ------------------
   ddr2_dq               : inout  std_logic_vector((DQ_WIDTH-1) downto 0);
   ddr2_a                : out   std_logic_vector((ROW_WIDTH-1) downto 0);
   ddr2_ba               : out   std_logic_vector((BANK_WIDTH-1) downto 0);
   ddr2_ras_n            : out   std_logic;
   ddr2_cas_n            : out   std_logic;
   ddr2_we_n             : out   std_logic;
   ddr2_cs_n             : out   std_logic_vector((CS_WIDTH-1) downto 0);
   ddr2_odt              : out   std_logic_vector((ODT_WIDTH-1) downto 0);
   ddr2_cke              : out   std_logic_vector((CKE_WIDTH-1) downto 0);
   ddr2_dm               : out   std_logic_vector((DM_WIDTH-1) downto 0);
   sys_clk_p             : in    std_logic;
   sys_clk_n             : in    std_logic;
   clk200_p              : in    std_logic;
   clk200_n              : in    std_logic;

   sys_rst_n             : in    std_logic;
   phy_init_done         : out   std_logic;
   ddr2_dqs              : inout  std_logic_vector((DQS_WIDTH-1) downto 0);
   ddr2_dqs_n            : inout  std_logic_vector((DQS_WIDTH-1) downto 0);
   ddr2_ck               : out   std_logic_vector((CLK_WIDTH-1) downto 0);
   ddr2_ck_n             : out   std_logic_vector((CLK_WIDTH-1) downto 0);
    -- ADD USER PORTS ABOVE THIS LINE ------------------

 

 where, again in red bolt font, you can see the signal grounded.

Finally, in the ucf file:

 

NET  "sys_clk_p"                                 LOC = "H17" ;          #Bank 3
NET  "sys_clk_n"                                 LOC = "H18" ;          #Bank 3
NET  "clk200_p"                                  LOC = "K17" ;          #Bank 3
NET  "clk200_n"                                  LOC = "L18" ;          #Bank 3

 

Message Edited by lucius1985 on 03-10-2010 08:22 AM
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7,708 Views
Registered: ‎04-09-2010

Hi,

 

I have the same problem.

Have you solve it ?

 

thanks

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xiaofeip_dup
Xilinx Employee
Xilinx Employee
7,705 Views
Registered: ‎08-07-2007

One question, did you allow PlatGen insert an I/O BUFFER automatically for those ports, in your custom EDK pcore?

 

BTW, what's the purpose of porting a MIG design to EDK with a PLB interface?  Doesn't MPMC serve the purpose?

 

-Felix

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Anonymous
Not applicable
6,965 Views

Hi,

    I too am facing the same problem. I created a Memory Interface instance thorugh MIG for DDR2 RAM. Now i am getting the same errors

ERROR : Xst : 2033   telling that Port I of ddr2_infrastructure / DIFF_ENDED_CLKS_INST.SYS_CLK_INST  is connected to ground.

similarly for IB and I and IB in  IDLY_CLK_INST.

 

Plese help me in this.  I m using xilinx ISE 12.1.

 

 

 

I have directly imported the component to my ISE project and passed signals to that. Just testing for the first time.

 

Thanks in advance.

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mam12
Visitor
Visitor
2,894 Views
Registered: ‎03-13-2016

HI, 

 

Even i am having same issue, can anybody solved this. please share the solution. 

 

 

ERROR:Xst:2033 - Port I of Input buffer u_DDR3/memc3_infrastructure_inst/diff_input_clk.u_ibufg_sys_clk is connected to GND
ERROR:Xst:2033 - Port IB of Input buffer u_DDR3/memc3_infrastructure_inst/diff_input_clk.u_ibufg_sys_clk is connected to GND
ERROR:Xst:1847 - Design checking failed

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prasanna_18
Contributor
Contributor
778 Views
Registered: ‎11-23-2018

Please check the input clock source properly driving or not ?.

From the top level module during the instantiation.

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