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Explorer
Explorer
8,349 Views
Registered: ‎01-25-2008

Post PAR files from EDK Run

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Hi,

 

Is it possible to generate some sort of post place and route netlist directly from EDK 14.7 without having to go to the hassle of creating a new ISE project?

 

Thanks.

Lachlan Grogan
CEO, SIL3 Pty Ltd
Melbourne, Australia
http://sil3.com.au
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1 Solution

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Community Manager
Community Manager
16,327 Views
Registered: ‎06-14-2012

Re: Post PAR files from EDK Run

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Yes you should be able to generate all post implementation ncd files and bitstream file from EDK/XPS project itself. 

These will be located in the implementation folder when you generate bitstream from the GUI.

 

http://www.xilinx.com/itp/xilinx10/help/platform_studio/ps_r_gst_xps_project_directories.htm 

Hope this helps.

Regards

Sikta

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3 Replies
Community Manager
Community Manager
16,328 Views
Registered: ‎06-14-2012

Re: Post PAR files from EDK Run

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Yes you should be able to generate all post implementation ncd files and bitstream file from EDK/XPS project itself. 

These will be located in the implementation folder when you generate bitstream from the GUI.

 

http://www.xilinx.com/itp/xilinx10/help/platform_studio/ps_r_gst_xps_project_directories.htm 

Hope this helps.

Regards

Sikta

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Explorer
Explorer
8,326 Views
Registered: ‎01-25-2008

Re: Post PAR files from EDK Run

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Hi,

Thanks for your response.

 

Do you know if there is an application note or otherwise showing how to use a tool like NetGen to take our top level NGC and some timing file (SDF?) and merge into a verilog or VHDL simulation file?

 

Thanks.

Lachlan Grogan
CEO, SIL3 Pty Ltd
Melbourne, Australia
http://sil3.com.au
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Community Manager
Community Manager
8,308 Views
Registered: ‎06-14-2012

Re: Post PAR files from EDK Run

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@lockiegrogan Glad that this is helpful.

 

This would be a different question. I would suggest creating a new thread in Simulation and verification board to get experts help.

On a general note,

  • For a functional netlist, use:

    netgen -ofmt {verilog|vhdl} [options] input_file[.ngd|ngc|ngo]
    
  • For a timing netlist and SDF, use:

    netgen -sim -ofmt {verilog|vhdl} [options] input_file[.ncd]
    

    (Refer to Xilinx’s UG628 Command Line Tools for detailed instructions on how to use this command).