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Participant
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Registered: ‎06-05-2009

PowerPC freezes when output to MDM when cache disabled

I' trying to use standart memory test (from examples).

No output (debug mode): it works

Output to UART: it works

Output to mdm and enabling data cache: it works.

 

Standart mode: Output to mdm and disabled data cache leads to error message: "Unable to STOP processor".

So, I need this mode, what kind of reasons can lead to this error.

 

Xilinx 14.4 Windows, Virtex 5 fx100t FPGA, bitstream for powerpc, works fine (ethernet for example), but not in

 

Thanks in advance.

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